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    <title>topic Re: NVMe device controller registers in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/NVMe-device-controller-registers/m-p/733931#M3124</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Probably it doesn't have memory-mapped registers? What problem do you see with the Linux driver?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 12 Mar 2018 13:24:00 GMT</pubDate>
    <dc:creator>adeel</dc:creator>
    <dc:date>2018-03-12T13:24:00Z</dc:date>
    <item>
      <title>NVMe device controller registers</title>
      <link>https://community.nxp.com/t5/Layerscape/NVMe-device-controller-registers/m-p/733929#M3122</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have written a PCIe driver for LS1046ardb and attached an NVMe based SS as PCIe device. When I read the memory region of System Memory Space where the PCIe device's memory is mapped, I can only read the NVMe controller register at offset 0x4. For the rest of the readonly fields, i get 0x0.&lt;/P&gt;&lt;P&gt;What is the possible reason that I can read one reg of NVMe rightly (0x3c013fff at offest 0x4) and find other wrong?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Iqra Javed&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 07 Mar 2018 07:35:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/NVMe-device-controller-registers/m-p/733929#M3122</guid>
      <dc:creator>iqrajaved</dc:creator>
      <dc:date>2018-03-07T07:35:13Z</dc:date>
    </item>
    <item>
      <title>Re: NVMe device controller registers</title>
      <link>https://community.nxp.com/t5/Layerscape/NVMe-device-controller-registers/m-p/733930#M3123</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The update is that some other PCIe devices like USB Host controller and BCM575 are read correctly with the same PCIe driver (RC mode) but there are issues in the case of NVMe based SSD.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Further, the other PCIe devices that are being read correctly are one lane devices while NVMe based SSD is multi-lane (2 lanes).&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can anyone guide me what must be the reason of this strange behavior?&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 07 Mar 2018 23:33:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/NVMe-device-controller-registers/m-p/733930#M3123</guid>
      <dc:creator>iqrajaved</dc:creator>
      <dc:date>2018-03-07T23:33:20Z</dc:date>
    </item>
    <item>
      <title>Re: NVMe device controller registers</title>
      <link>https://community.nxp.com/t5/Layerscape/NVMe-device-controller-registers/m-p/733931#M3124</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Probably it doesn't have memory-mapped registers? What problem do you see with the Linux driver?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Mar 2018 13:24:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/NVMe-device-controller-registers/m-p/733931#M3124</guid>
      <dc:creator>adeel</dc:creator>
      <dc:date>2018-03-12T13:24:00Z</dc:date>
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