topic Re: Can you support multiple Layerscape devices with a single PBL/PBI? in Layerscape

Can you support multiple Layerscape devices with a single PBL/PBI?

erichhoover — Wed, 17 Jan 2018 20:10:45 GMT

It looks like we may be in the unfortunate position of having to support two different Layerscape devices (LS1046A and possibly the LS2088A). Our current design has us reading the RCW from an SD card, so what I would like to be able to do is construct a PBL/PBI that can boot either chip. It looks like there are PBL mechanisms to do conditional instructions, so is it possible to do something like this?

Re: Can you support multiple Layerscape devices with a single PBL/PBI?

alexander_yakov — Thu, 18 Jan 2018 06:25:25 GMT

No, PBL does not support any conditional instructions, it is quite simple - address, number of bytes, and data itself.

Have a great day,
Alexander
TIC

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Re: Can you support multiple Layerscape devices with a single PBL/PBI?

erichhoover — Thu, 18 Jan 2018 15:44:23 GMT

Not to be contrary, but the LS2088A reference manual says that PBI command 0x85 performs a conditional jump. The problem I see is that the LS1046A has a completely different command set (writing to 0x61_0000 + offset, and has jump but no conditional jump), and it's not entirely clear to me what would happen if I mix and match commands between the two. It seems like it might be possible to cobble together a set of commands that one processor would ignore but the other one would accept, allowing me to load the appropriate RCW for each processor.

The other thing I was looking at is whether I can possibly simply send both RCW writes, since they have different addresses between the two processors (0x1EE_0100 for the LS1046A and 0x1E0_0100 for the LS2088A) and the "wrong" address for each processor is in a reserved section of memory. However, even the write syntax appears to be slightly different between the two (0x01EE0100 would feed an invalid "B" value of 0 for the LS2088A and 0x31E00100 would feed an invalid byte count of 24 to the LS1046A). It's not obvious to me what happens if I write to a reserved section of memory, or what happens if I feed invalid B/"byte count" values.

So, not really caring how it's achieved, what I'm really hoping is that there is some way to boot both processors with the same system image. I can experiment with this some on my own here soon, but it seems like a problem that other people have likely encountered and figured out already.