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    <title>topic ls1021a pcie in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/ls1021a-pcie/m-p/719560#M2976</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hello experts，&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; I have ls1021a custom board. when the kernel boot, it sometimes hangs up&amp;nbsp;in pcie. The following is kernel boot log.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Booting Linux on physical CPU 0xf00 &lt;BR /&gt;Linux version 4.1.35-rt41 (splin@splin-VirtualBox) (gcc version 4.9.3 20150311 (&lt;BR /&gt;prerelease) (Linaro GCC 4.9-2015.03) ) #1 SMP Fri Feb 2 10:14:17 CST 2018 &lt;BR /&gt;CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=70c5387d &lt;BR /&gt;CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache &lt;BR /&gt;Machine model: LS1021A TWR Board &lt;BR /&gt;earlycon: Early serial console at MMIO 0x21c0500 (options '') &lt;BR /&gt;bootconsole [uart0] enabled &lt;BR /&gt;Booting Linux on physical CPU 0xf00 &lt;BR /&gt;Linux version 4.1.35-rt41 (splin@splin-VirtualBox) (gcc version 4.9.3 20150311 (&lt;BR /&gt;prerelease) (Linaro GCC 4.9-2015.03) ) #1 SMP Fri Feb 2 10:14:17 CST 2018 &lt;BR /&gt;CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=70c5387d &lt;BR /&gt;CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache &lt;BR /&gt;Machine model: LS1021A TWR Board &lt;BR /&gt;earlycon: Early serial console at MMIO 0x21c0500 (options '') &lt;BR /&gt;bootconsole [uart0] enabled &lt;BR /&gt;bootconsole [earlycon0] enabled &lt;BR /&gt;bootconsole [earlycon0] enabled &lt;BR /&gt;Forcing write-allocate cache policy for SMP &lt;BR /&gt;Forcing write-allocate cache policy for SMP &lt;BR /&gt;Memory policy: Data cache writealloc &lt;BR /&gt;Memory policy: Data cache writealloc &lt;BR /&gt;psci: probing for conduit method from DT. &lt;BR /&gt;psci: probing for conduit method from DT. &lt;BR /&gt;psci: PSCIv1.0 detected in firmware. &lt;BR /&gt;psci: PSCIv1.0 detected in firmware. &lt;BR /&gt;psci: Using standard PSCI v0.2 function IDs &lt;BR /&gt;psci: Using standard PSCI v0.2 function IDs &lt;BR /&gt;PERCPU: Embedded 12 pages/cpu @ee7c7000 s16640 r8192 d24320 u49152 &lt;BR /&gt;PERCPU: Embedded 12 pages/cpu @ee7c7000 s16640 r8192 d24320 u49152 &lt;BR /&gt;Built 1 zonelists in Zone order, mobility grouping on. Total pages: 520720 &lt;BR /&gt;Built 1 zonelists in Zone order, mobility grouping on. Total pages: 520720 &lt;BR /&gt;Kernel command line: root=/dev/ram rw ramdisk_size=40000000 console=ttyS0,115200&lt;BR /&gt; earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 earlyprintk &lt;BR /&gt;Kernel command line: root=/dev/ram rw ramdisk_size=40000000 console=ttyS0,115200&lt;BR /&gt; earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 earlyprintk &lt;BR /&gt;PID hash table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;PID hash table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;Dentry cache hash table entries: 262144 (order: 8, 1048576 bytes) &lt;BR /&gt;Dentry cache hash table entries: 262144 (order: 8, 1048576 bytes) &lt;BR /&gt;Inode-cache hash table entries: 131072 (order: 7, 524288 bytes) &lt;BR /&gt;Inode-cache hash table entries: 131072 (order: 7, 524288 bytes) &lt;BR /&gt;Memory: 2048228K/2097152K available (3724K kernel code, 246K rwdata, 1732K rodat&lt;BR /&gt;a, 252K init, 210K bss, 48924K reserved, 0K cma-reserved, 270336K highmem) &lt;BR /&gt;Memory: 2048228K/2097152K available (3724K kernel code, 246K rwdata, 1732K rodat&lt;BR /&gt;a, 252K init, 210K bss, 48924K reserved, 0K cma-reserved, 270336K highmem) &lt;BR /&gt;Virtual kernel memory layout: &lt;BR /&gt; vector : 0xffff0000 - 0xffff1000 ( 4 kB) &lt;BR /&gt; fixmap : 0xffc00000 - 0xfff00000 (3072 kB) &lt;BR /&gt; vmalloc : 0xf0000000 - 0xff000000 ( 240 MB) &lt;BR /&gt; lowmem : 0x80000000 - 0xef800000 (1784 MB) &lt;BR /&gt; pkmap : 0x7fe00000 - 0x80000000 ( 2 MB) &lt;BR /&gt; modules : 0x7f800000 - 0x7fe00000 ( 6 MB) &lt;BR /&gt; .text : 0x80008000 - 0x8055c5bc (5458 kB) &lt;BR /&gt; .init : 0x8055d000 - 0x8059c000 ( 252 kB) &lt;BR /&gt; .data : 0x8059c000 - 0x805d9928 ( 247 kB) &lt;BR /&gt; .bss : 0x805dc000 - 0x80610864 ( 211 kB) &lt;BR /&gt;Virtual kernel memory layout: &lt;BR /&gt; vector : 0xffff0000 - 0xffff1000 ( 4 kB) &lt;BR /&gt; fixmap : 0xffc00000 - 0xfff00000 (3072 kB) &lt;BR /&gt; vmalloc : 0xf0000000 - 0xff000000 ( 240 MB) &lt;BR /&gt; lowmem : 0x80000000 - 0xef800000 (1784 MB) &lt;BR /&gt; pkmap : 0x7fe00000 - 0x80000000 ( 2 MB) &lt;BR /&gt; modules : 0x7f800000 - 0x7fe00000 ( 6 MB) &lt;BR /&gt; .text : 0x80008000 - 0x8055c5bc (5458 kB) &lt;BR /&gt; .init : 0x8055d000 - 0x8059c000 ( 252 kB) &lt;BR /&gt; .data : 0x8059c000 - 0x805d9928 ( 247 kB) &lt;BR /&gt; .bss : 0x805dc000 - 0x80610864 ( 211 kB) &lt;BR /&gt;SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 &lt;BR /&gt;SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 &lt;BR /&gt;Hierarchical RCU implementation. &lt;BR /&gt;Hierarchical RCU implementation. &lt;BR /&gt; Additional per-CPU info printed with stalls. &lt;BR /&gt; Additional per-CPU info printed with stalls. &lt;BR /&gt; RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. &lt;BR /&gt; RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. &lt;BR /&gt;RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 &lt;BR /&gt;RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 &lt;BR /&gt;NR_IRQS:16 nr_irqs:16 16 &lt;BR /&gt;NR_IRQS:16 nr_irqs:16 16 &lt;BR /&gt;Architected cp15 timer(s) running at 12.50MHz (phys). &lt;BR /&gt;Architected cp15 timer(s) running at 12.50MHz (phys). &lt;BR /&gt;clocksource arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049cda, ma&lt;BR /&gt;x_idle_ns: 440795202628 ns &lt;BR /&gt;clocksource arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049cda, ma&lt;BR /&gt;x_idle_ns: 440795202628 ns &lt;BR /&gt;sched_clock: 56 bits at 12MHz, resolution 80ns, wraps every 4398046511080ns &lt;BR /&gt;sched_clock: 56 bits at 12MHz, resolution 80ns, wraps every 4398046511080ns &lt;BR /&gt;Switching to timer-based delay loop, resolution 80ns &lt;BR /&gt;Switching to timer-based delay loop, resolution 80ns &lt;BR /&gt;Console: colour dummy device 80x30 &lt;BR /&gt;Console: colour dummy device 80x30 &lt;BR /&gt;Calibrating delay loop (skipped), value calculated using timer frequency.. Calib&lt;BR /&gt;rating delay loop (skipped), value calculated using timer frequency.. 25.00 Bogo&lt;BR /&gt;MIPS (lpj=125000) &lt;BR /&gt;25.00 BogoMIPS (lpj=125000) &lt;BR /&gt;pid_max: default: 32768 minimum: 301 &lt;BR /&gt;pid_max: default: 32768 minimum: 301 &lt;BR /&gt;Mount-cache hhsh table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;Mount-cache hash table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;Mountpoint-cache hash table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;Mountpoint-cache hash table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;CPU: Testing write buffer coherency: CPU: Testing write buffer coherency: ok &lt;BR /&gt;ok &lt;BR /&gt;CPU0: update cpu_capacity 1024 &lt;BR /&gt;CPU0: update cpu_capacity 1024 &lt;BR /&gt;CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 &lt;BR /&gt;CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 &lt;BR /&gt;Setting up static identity map for 0x800082c0 - 0x80008324 &lt;BR /&gt;Setting up static identity map for 0x800082c0 - 0x80008324 &lt;BR /&gt;CPU1: update cpu_capacity 1024 &lt;BR /&gt;CPU1: update cpu_capacity 1024 &lt;BR /&gt;CPU1: thread -1, cpu 1, socket 15, mpidr 80000f01 &lt;BR /&gt;CPU1: thread -1, cpu 1, socket 15, mpidr 80000f01 &lt;BR /&gt;Brought up 2 CPUs &lt;BR /&gt;Brought up 2 CPUs &lt;BR /&gt;SMP: Total of 2 processors activated (50.00 BogoMIPS). &lt;BR /&gt;SMP: Total of 2 processors activated (50.00 BogoMIPS). &lt;BR /&gt;CPU: All CPU(s) started in HYP mode. &lt;BR /&gt;CPU: All CPU(s) started in HYP mode. &lt;BR /&gt;CPU: Virtualization extensions available. &lt;BR /&gt;CPU: Virtualization extensions available. &lt;BR /&gt;devtmpfs: initialized &lt;BR /&gt;devtmpfs: initialized &lt;BR /&gt;VFP support v0.3: VFP support v0.3: implementor 41 architecture 2 part 30 varian&lt;BR /&gt;t 7 rev 5 &lt;BR /&gt;implementor 41 architecture 2 part 30 variant 7 rev 5 &lt;BR /&gt;clocksource jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112&lt;BR /&gt;604462750000 ns &lt;BR /&gt;clocksource jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112&lt;BR /&gt;604462750000 ns &lt;BR /&gt;pinctrl core: initialized pinctrl subsystem &lt;BR /&gt;pinctrl core: initialized pinctrl subsystem &lt;BR /&gt;NET: Registered protocol family 16 &lt;BR /&gt;NET: Registered protocol family 16 &lt;BR /&gt;DMA: preallocated 256 KiB pool for atomic coherent allocations &lt;BR /&gt;DMA: preallocated 256 KiB pool for atomic coherent allocations &lt;BR /&gt;cpuidle: using governor ladder &lt;BR /&gt;cpuidle: using governor ladder &lt;BR /&gt;cpuidle: using governor menu &lt;BR /&gt;cpuidle: using governor menu &lt;BR /&gt;Machine: LS1021A TWR Board &lt;BR /&gt;Machine: LS1021A TWRRBoard &lt;BR /&gt;SoC family: QorIQ LS1021A &lt;BR /&gt;SoC family: QorIQ LS1021A &lt;BR /&gt;SoC ID: svr:0x87080020, Revision: 2.0 &lt;BR /&gt;SoC ID: svr:0x87080020, Revision: 2.0 &lt;BR /&gt;irq: no irq domain found for /soc/uqe@2400000/qeic@80 ! &lt;BR /&gt;irq: no irq domain found for /soc/uqe@2400000/qeic@80 ! &lt;BR /&gt;irq: no irq domain found for /soc/uqe@2400000/qeic@80 ! &lt;BR /&gt;irq: no irq domain found for /soc/uqe@2400000/qeic@80 ! &lt;BR /&gt;hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers. &lt;BR /&gt;hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers. &lt;BR /&gt;hw-breakpoint: maximum watchpoint size is 8 bytes. &lt;BR /&gt;hw-breakpoint: maximum watchpoint size is 8 bytes. &lt;BR /&gt;register e1000-wakeup irq error, ret = -22 &lt;BR /&gt;register e1000-wakeup irq error, ret = -22 &lt;BR /&gt;Serial: AMBA PL011 UART driver &lt;BR /&gt;Serial: AMBA PL011 UART driver &lt;BR /&gt;RCPM: layerscape_rcpm_init: Fail to get "fsl,#rcpm-wakeup-cells". &lt;BR /&gt;RCPM: layerscape_rcpm_init: Fail to get "fsl,#rcpm-wakeup-cells". &lt;BR /&gt;vgaarb: loaded &lt;BR /&gt;vgaarb: loaded &lt;BR /&gt;SCSI subsystem initialized &lt;BR /&gt;SCSI subsystem initialized &lt;BR /&gt;usbcore: registered new interface driver usbfs &lt;BR /&gt;usbcore: registered new interface driver usbfs &lt;BR /&gt;usbcore: registered new interface driver hub &lt;BR /&gt;usbcore: registered new interface driver hub &lt;BR /&gt;usbcore: registered new device driver usb &lt;BR /&gt;usbcore: registered new device driver usb &lt;BR /&gt;i2c i2c-0: IMX I2C adapter registered &lt;BR /&gt;i2c i2c-0: IMX I2C adapter registered &lt;BR /&gt;i2c i2c-0: can't use DMA &lt;BR /&gt;i2c i2c-0: can't use DMA &lt;BR /&gt;i2c i2c-1: IMX I2C adapter registered &lt;BR /&gt;i2c i2c-1: IMX I2C adapter registered &lt;BR /&gt;i2c i2c-1: can't use DMA &lt;BR /&gt;i2c i2c-1: can't use DMA &lt;BR /&gt;pps_core: LinuxPPS API ver. 1 registered &lt;BR /&gt;pps_core: LinuxPPS API ver. 1 registered &lt;BR /&gt;pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti &amp;lt;giometti@l&lt;BR /&gt;inux.it&amp;gt; &lt;BR /&gt;pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti &amp;lt;giometti@l&lt;BR /&gt;inux.it&amp;gt; &lt;BR /&gt;PTP clock support registered &lt;BR /&gt;PTP clock support registered &lt;BR /&gt;fsl-ifc 1530000.ifc: Freescale Integrated Flash Controller &lt;BR /&gt;fsl-ifc 1530000.ifc: Freescale Integrated Flash Controller &lt;BR /&gt;fsl-ifc 1530000.ifc: IFC version 1.4, 8 banks &lt;BR /&gt;fsl-ifc 1530000.ifc: IFC version 1.4, 8 banks &lt;BR /&gt;Advanced Linux Sound Architecture Driver Initialized. &lt;BR /&gt;Advanced Linux Sound Architecture Driver Initialized. &lt;BR /&gt;Switched to clocksource arch_sys_counter &lt;BR /&gt;Switched to clocksource arch_sys_counter &lt;BR /&gt;NET: Registered protocol family 2 &lt;BR /&gt;NET: Registered protocol family 2 &lt;BR /&gt;TCP established hash table entries: 16384 (order: 4, 65536 bytes) &lt;BR /&gt;TCP established hash table entries: 16384 (order: 4, 65536 bytes) &lt;BR /&gt;TCP bind hash table entries: 16384 (order: 5, 131072 bytes) &lt;BR /&gt;TCP bind hash table entries: 16384 (order: 5, 131072 bytes) &lt;BR /&gt;TCP: Hash tables configured (established 16384 bind 16384) &lt;BR /&gt;TCP: Hash tables configured (established 16384 bind 16384) &lt;BR /&gt;UDP hash table entries: 1024 (order: 3, 32768 bytes) &lt;BR /&gt;UDP hash table entries: 1024 (order: 3, 32768 bytes) &lt;BR /&gt;UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes) &lt;BR /&gt;UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes) &lt;BR /&gt;NET: Registered protocol family 1 &lt;BR /&gt;NET: Registered protocol family 1 &lt;BR /&gt;RPC: Registered named UNIX socket transport module. &lt;BR /&gt;RPC: Registered named UNIX socket transport module. &lt;BR /&gt;RPC: Registered udp transport module. &lt;BR /&gt;RPC: Registered udp transport module. &lt;BR /&gt;RPC: Registered tcp transport module. &lt;BR /&gt;RPC: Registered tcp transport module. &lt;BR /&gt;RPC: Registered tcp NFSv4.1 backchannel transport module. &lt;BR /&gt;RPC: Registered tcp NFSv4.1 backchannel transport module. &lt;BR /&gt;Trying to unpack rootfs image as initramfs... &lt;BR /&gt;Trying to unpack rootfs image as initramfs... &lt;BR /&gt;rootfs image is not initramfs (no cpio magic); looks like an initrd &lt;BR /&gt;rootfs image is not initramfs (no cpio magic); looks like an initrd &lt;BR /&gt;Freeing initrd memory: 22488K (88000000 - 895f6000) &lt;BR /&gt;Freeing initrd memory: 22488K (88000000 - 895f6000) &lt;BR /&gt;kvm [1]: interrupt-controller@1404000 IRQ22 &lt;BR /&gt;kvm [1]: interrupt-controller@1404000 IRQ22 &lt;BR /&gt;kvm [1]: timer IRQ18 &lt;BR /&gt;kvm [1]: timer IRQ18 &lt;BR /&gt;kvm [1]: Hyp mode initialized successfully &lt;BR /&gt;kvm [1]: Hyp mode initialized successfully &lt;BR /&gt;CPU PMU: Failed to parse /pmu/interrupt-affinity[0] &lt;BR /&gt;CPU PMU: Failed to parse /pmu/interrupt-affinity[0] &lt;BR /&gt;hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available &lt;BR /&gt;hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available &lt;BR /&gt;futex hash table entries: 512 (order: 3, 32768 bytes) &lt;BR /&gt;futex hash table entries: 512 (order: 3, 32768 bytes) &lt;BR /&gt;HugeTLB registered 2 MB page size, pre-allocated 0 pages &lt;BR /&gt;HugeTLB registered 2 MB page size, pre-allocated 0 pages &lt;BR /&gt;NFS: Registering the id_resolver key type &lt;BR /&gt;NFS: Registering the id_resolver key type &lt;BR /&gt;Key type id_resolver registered &lt;BR /&gt;Key type id_resolver registered &lt;BR /&gt;Key type id_legacy registered &lt;BR /&gt;Key type id_legacy registered &lt;BR /&gt;jffs2: version 2.2. (NAND) 漏 2001-2006 Red Hat, Inc. &lt;BR /&gt;jffs2: version 2.2. (NAND) 漏 2001-2006 Red Hat, Inc. &lt;BR /&gt;bounce: pool size: 64 pages &lt;BR /&gt;bounce: pool size: 64 pages &lt;BR /&gt;io scheduler noop registered &lt;BR /&gt;io scheduler noop registered &lt;BR /&gt;io scheduler deadline registered &lt;BR /&gt;io scheduler deadline registered &lt;BR /&gt;io scheduler cfq registered (default) &lt;BR /&gt;io scheduler cfq registered (default) &lt;BR /&gt;ls-scfg-msi soc:msi-controller: ibs_shift:3 msir_irqs:32 msir_base:0x4 &lt;BR /&gt;ls-scfg-msi soc:msi-controller: ibs_shift:3 msir_irqs:32 msir_base:0x4 &lt;BR /&gt;Find msi-controller /soc/msi-controller &lt;BR /&gt;Find msi-controller /soc/msi-controller &lt;BR /&gt;PCI host bridge /soc/pcie@3400000 ranges: &lt;BR /&gt;PCI host bridge /soc/pcie@3400000 ranges: &lt;BR /&gt; IO 0x4000010000..0x400001ffff -&amp;gt; 0x00000000 &lt;BR /&gt; IO 0x4000010000..0x400001ffff -&amp;gt; 0x00000000 &lt;BR /&gt; MEM 0x4040000000..0x407fffffff -&amp;gt; 0x40000000 &lt;BR /&gt; MEM 0x4040000000..0x407fffffff -&amp;gt; 0x40000000 &lt;BR /&gt;layerscape-pcie 3400000.pcie: PCI host bridge to bus 0000:00 &lt;BR /&gt;layerscape-pcie 3400000.pcie: PCI host bridge to bus 0000:00 &lt;BR /&gt;pci_bus 0000:00: root bus resource [bus 00-ff] &lt;BR /&gt;pci_bus 0000:00: root bus resource [bus 00-ff] &lt;BR /&gt;pci_bus 0000:00: root bus resource [io 0x0000-0xffff] &lt;BR /&gt;pci_bus 0000:00: root bus resource [io 0x0000-0xffff] &lt;BR /&gt;pci_bus 0000:00: root bus resource [mem 0x4040000000-0x407fffffff] (bus address &lt;BR /&gt;[0x40000000-0x7fffffff]) &lt;BR /&gt;pci_bus 0000:00: root bus resource [mem 0x4040000000-0x407fffffff] (bus address &lt;BR /&gt;[0x40000000-0x7fffffff]) &lt;BR /&gt;PCI: bus0: Fast back to back transfers disabled &lt;BR /&gt;PCI: bus0: Fast back to back transfers disabled &lt;BR /&gt;PCI: bus1: Fast back to back transfers enabled &lt;BR /&gt;PCI: bus1: Fast back to back transfers enabled &lt;BR /&gt;pci 0000:00:00.0: BAR 6: assigned [mem 0x4040000000-0x40400007ff pref] &lt;BR /&gt;pci 0000:00:00.0: BAR 6: assigned [mem 0x4040000000-0x40400007ff pref] &lt;BR /&gt;pci 0000:00:00.0: PCI bridge to [bus 01] &lt;BR /&gt;pci 0000:00:00.0: PCI bridge to [bus 01]&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 06 Feb 2018 01:54:21 GMT</pubDate>
    <dc:creator>shunpinglin</dc:creator>
    <dc:date>2018-02-06T01:54:21Z</dc:date>
    <item>
      <title>ls1021a pcie</title>
      <link>https://community.nxp.com/t5/Layerscape/ls1021a-pcie/m-p/719560#M2976</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hello experts，&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; I have ls1021a custom board. when the kernel boot, it sometimes hangs up&amp;nbsp;in pcie. The following is kernel boot log.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Booting Linux on physical CPU 0xf00 &lt;BR /&gt;Linux version 4.1.35-rt41 (splin@splin-VirtualBox) (gcc version 4.9.3 20150311 (&lt;BR /&gt;prerelease) (Linaro GCC 4.9-2015.03) ) #1 SMP Fri Feb 2 10:14:17 CST 2018 &lt;BR /&gt;CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=70c5387d &lt;BR /&gt;CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache &lt;BR /&gt;Machine model: LS1021A TWR Board &lt;BR /&gt;earlycon: Early serial console at MMIO 0x21c0500 (options '') &lt;BR /&gt;bootconsole [uart0] enabled &lt;BR /&gt;Booting Linux on physical CPU 0xf00 &lt;BR /&gt;Linux version 4.1.35-rt41 (splin@splin-VirtualBox) (gcc version 4.9.3 20150311 (&lt;BR /&gt;prerelease) (Linaro GCC 4.9-2015.03) ) #1 SMP Fri Feb 2 10:14:17 CST 2018 &lt;BR /&gt;CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=70c5387d &lt;BR /&gt;CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache &lt;BR /&gt;Machine model: LS1021A TWR Board &lt;BR /&gt;earlycon: Early serial console at MMIO 0x21c0500 (options '') &lt;BR /&gt;bootconsole [uart0] enabled &lt;BR /&gt;bootconsole [earlycon0] enabled &lt;BR /&gt;bootconsole [earlycon0] enabled &lt;BR /&gt;Forcing write-allocate cache policy for SMP &lt;BR /&gt;Forcing write-allocate cache policy for SMP &lt;BR /&gt;Memory policy: Data cache writealloc &lt;BR /&gt;Memory policy: Data cache writealloc &lt;BR /&gt;psci: probing for conduit method from DT. &lt;BR /&gt;psci: probing for conduit method from DT. &lt;BR /&gt;psci: PSCIv1.0 detected in firmware. &lt;BR /&gt;psci: PSCIv1.0 detected in firmware. &lt;BR /&gt;psci: Using standard PSCI v0.2 function IDs &lt;BR /&gt;psci: Using standard PSCI v0.2 function IDs &lt;BR /&gt;PERCPU: Embedded 12 pages/cpu @ee7c7000 s16640 r8192 d24320 u49152 &lt;BR /&gt;PERCPU: Embedded 12 pages/cpu @ee7c7000 s16640 r8192 d24320 u49152 &lt;BR /&gt;Built 1 zonelists in Zone order, mobility grouping on. Total pages: 520720 &lt;BR /&gt;Built 1 zonelists in Zone order, mobility grouping on. Total pages: 520720 &lt;BR /&gt;Kernel command line: root=/dev/ram rw ramdisk_size=40000000 console=ttyS0,115200&lt;BR /&gt; earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 earlyprintk &lt;BR /&gt;Kernel command line: root=/dev/ram rw ramdisk_size=40000000 console=ttyS0,115200&lt;BR /&gt; earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 earlyprintk &lt;BR /&gt;PID hash table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;PID hash table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;Dentry cache hash table entries: 262144 (order: 8, 1048576 bytes) &lt;BR /&gt;Dentry cache hash table entries: 262144 (order: 8, 1048576 bytes) &lt;BR /&gt;Inode-cache hash table entries: 131072 (order: 7, 524288 bytes) &lt;BR /&gt;Inode-cache hash table entries: 131072 (order: 7, 524288 bytes) &lt;BR /&gt;Memory: 2048228K/2097152K available (3724K kernel code, 246K rwdata, 1732K rodat&lt;BR /&gt;a, 252K init, 210K bss, 48924K reserved, 0K cma-reserved, 270336K highmem) &lt;BR /&gt;Memory: 2048228K/2097152K available (3724K kernel code, 246K rwdata, 1732K rodat&lt;BR /&gt;a, 252K init, 210K bss, 48924K reserved, 0K cma-reserved, 270336K highmem) &lt;BR /&gt;Virtual kernel memory layout: &lt;BR /&gt; vector : 0xffff0000 - 0xffff1000 ( 4 kB) &lt;BR /&gt; fixmap : 0xffc00000 - 0xfff00000 (3072 kB) &lt;BR /&gt; vmalloc : 0xf0000000 - 0xff000000 ( 240 MB) &lt;BR /&gt; lowmem : 0x80000000 - 0xef800000 (1784 MB) &lt;BR /&gt; pkmap : 0x7fe00000 - 0x80000000 ( 2 MB) &lt;BR /&gt; modules : 0x7f800000 - 0x7fe00000 ( 6 MB) &lt;BR /&gt; .text : 0x80008000 - 0x8055c5bc (5458 kB) &lt;BR /&gt; .init : 0x8055d000 - 0x8059c000 ( 252 kB) &lt;BR /&gt; .data : 0x8059c000 - 0x805d9928 ( 247 kB) &lt;BR /&gt; .bss : 0x805dc000 - 0x80610864 ( 211 kB) &lt;BR /&gt;Virtual kernel memory layout: &lt;BR /&gt; vector : 0xffff0000 - 0xffff1000 ( 4 kB) &lt;BR /&gt; fixmap : 0xffc00000 - 0xfff00000 (3072 kB) &lt;BR /&gt; vmalloc : 0xf0000000 - 0xff000000 ( 240 MB) &lt;BR /&gt; lowmem : 0x80000000 - 0xef800000 (1784 MB) &lt;BR /&gt; pkmap : 0x7fe00000 - 0x80000000 ( 2 MB) &lt;BR /&gt; modules : 0x7f800000 - 0x7fe00000 ( 6 MB) &lt;BR /&gt; .text : 0x80008000 - 0x8055c5bc (5458 kB) &lt;BR /&gt; .init : 0x8055d000 - 0x8059c000 ( 252 kB) &lt;BR /&gt; .data : 0x8059c000 - 0x805d9928 ( 247 kB) &lt;BR /&gt; .bss : 0x805dc000 - 0x80610864 ( 211 kB) &lt;BR /&gt;SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 &lt;BR /&gt;SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 &lt;BR /&gt;Hierarchical RCU implementation. &lt;BR /&gt;Hierarchical RCU implementation. &lt;BR /&gt; Additional per-CPU info printed with stalls. &lt;BR /&gt; Additional per-CPU info printed with stalls. &lt;BR /&gt; RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. &lt;BR /&gt; RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. &lt;BR /&gt;RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 &lt;BR /&gt;RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 &lt;BR /&gt;NR_IRQS:16 nr_irqs:16 16 &lt;BR /&gt;NR_IRQS:16 nr_irqs:16 16 &lt;BR /&gt;Architected cp15 timer(s) running at 12.50MHz (phys). &lt;BR /&gt;Architected cp15 timer(s) running at 12.50MHz (phys). &lt;BR /&gt;clocksource arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049cda, ma&lt;BR /&gt;x_idle_ns: 440795202628 ns &lt;BR /&gt;clocksource arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049cda, ma&lt;BR /&gt;x_idle_ns: 440795202628 ns &lt;BR /&gt;sched_clock: 56 bits at 12MHz, resolution 80ns, wraps every 4398046511080ns &lt;BR /&gt;sched_clock: 56 bits at 12MHz, resolution 80ns, wraps every 4398046511080ns &lt;BR /&gt;Switching to timer-based delay loop, resolution 80ns &lt;BR /&gt;Switching to timer-based delay loop, resolution 80ns &lt;BR /&gt;Console: colour dummy device 80x30 &lt;BR /&gt;Console: colour dummy device 80x30 &lt;BR /&gt;Calibrating delay loop (skipped), value calculated using timer frequency.. Calib&lt;BR /&gt;rating delay loop (skipped), value calculated using timer frequency.. 25.00 Bogo&lt;BR /&gt;MIPS (lpj=125000) &lt;BR /&gt;25.00 BogoMIPS (lpj=125000) &lt;BR /&gt;pid_max: default: 32768 minimum: 301 &lt;BR /&gt;pid_max: default: 32768 minimum: 301 &lt;BR /&gt;Mount-cache hhsh table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;Mount-cache hash table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;Mountpoint-cache hash table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;Mountpoint-cache hash table entries: 4096 (order: 2, 16384 bytes) &lt;BR /&gt;CPU: Testing write buffer coherency: CPU: Testing write buffer coherency: ok &lt;BR /&gt;ok &lt;BR /&gt;CPU0: update cpu_capacity 1024 &lt;BR /&gt;CPU0: update cpu_capacity 1024 &lt;BR /&gt;CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 &lt;BR /&gt;CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00 &lt;BR /&gt;Setting up static identity map for 0x800082c0 - 0x80008324 &lt;BR /&gt;Setting up static identity map for 0x800082c0 - 0x80008324 &lt;BR /&gt;CPU1: update cpu_capacity 1024 &lt;BR /&gt;CPU1: update cpu_capacity 1024 &lt;BR /&gt;CPU1: thread -1, cpu 1, socket 15, mpidr 80000f01 &lt;BR /&gt;CPU1: thread -1, cpu 1, socket 15, mpidr 80000f01 &lt;BR /&gt;Brought up 2 CPUs &lt;BR /&gt;Brought up 2 CPUs &lt;BR /&gt;SMP: Total of 2 processors activated (50.00 BogoMIPS). &lt;BR /&gt;SMP: Total of 2 processors activated (50.00 BogoMIPS). &lt;BR /&gt;CPU: All CPU(s) started in HYP mode. &lt;BR /&gt;CPU: All CPU(s) started in HYP mode. &lt;BR /&gt;CPU: Virtualization extensions available. &lt;BR /&gt;CPU: Virtualization extensions available. &lt;BR /&gt;devtmpfs: initialized &lt;BR /&gt;devtmpfs: initialized &lt;BR /&gt;VFP support v0.3: VFP support v0.3: implementor 41 architecture 2 part 30 varian&lt;BR /&gt;t 7 rev 5 &lt;BR /&gt;implementor 41 architecture 2 part 30 variant 7 rev 5 &lt;BR /&gt;clocksource jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112&lt;BR /&gt;604462750000 ns &lt;BR /&gt;clocksource jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112&lt;BR /&gt;604462750000 ns &lt;BR /&gt;pinctrl core: initialized pinctrl subsystem &lt;BR /&gt;pinctrl core: initialized pinctrl subsystem &lt;BR /&gt;NET: Registered protocol family 16 &lt;BR /&gt;NET: Registered protocol family 16 &lt;BR /&gt;DMA: preallocated 256 KiB pool for atomic coherent allocations &lt;BR /&gt;DMA: preallocated 256 KiB pool for atomic coherent allocations &lt;BR /&gt;cpuidle: using governor ladder &lt;BR /&gt;cpuidle: using governor ladder &lt;BR /&gt;cpuidle: using governor menu &lt;BR /&gt;cpuidle: using governor menu &lt;BR /&gt;Machine: LS1021A TWR Board &lt;BR /&gt;Machine: LS1021A TWRRBoard &lt;BR /&gt;SoC family: QorIQ LS1021A &lt;BR /&gt;SoC family: QorIQ LS1021A &lt;BR /&gt;SoC ID: svr:0x87080020, Revision: 2.0 &lt;BR /&gt;SoC ID: svr:0x87080020, Revision: 2.0 &lt;BR /&gt;irq: no irq domain found for /soc/uqe@2400000/qeic@80 ! &lt;BR /&gt;irq: no irq domain found for /soc/uqe@2400000/qeic@80 ! &lt;BR /&gt;irq: no irq domain found for /soc/uqe@2400000/qeic@80 ! &lt;BR /&gt;irq: no irq domain found for /soc/uqe@2400000/qeic@80 ! &lt;BR /&gt;hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers. &lt;BR /&gt;hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers. &lt;BR /&gt;hw-breakpoint: maximum watchpoint size is 8 bytes. &lt;BR /&gt;hw-breakpoint: maximum watchpoint size is 8 bytes. &lt;BR /&gt;register e1000-wakeup irq error, ret = -22 &lt;BR /&gt;register e1000-wakeup irq error, ret = -22 &lt;BR /&gt;Serial: AMBA PL011 UART driver &lt;BR /&gt;Serial: AMBA PL011 UART driver &lt;BR /&gt;RCPM: layerscape_rcpm_init: Fail to get "fsl,#rcpm-wakeup-cells". &lt;BR /&gt;RCPM: layerscape_rcpm_init: Fail to get "fsl,#rcpm-wakeup-cells". &lt;BR /&gt;vgaarb: loaded &lt;BR /&gt;vgaarb: loaded &lt;BR /&gt;SCSI subsystem initialized &lt;BR /&gt;SCSI subsystem initialized &lt;BR /&gt;usbcore: registered new interface driver usbfs &lt;BR /&gt;usbcore: registered new interface driver usbfs &lt;BR /&gt;usbcore: registered new interface driver hub &lt;BR /&gt;usbcore: registered new interface driver hub &lt;BR /&gt;usbcore: registered new device driver usb &lt;BR /&gt;usbcore: registered new device driver usb &lt;BR /&gt;i2c i2c-0: IMX I2C adapter registered &lt;BR /&gt;i2c i2c-0: IMX I2C adapter registered &lt;BR /&gt;i2c i2c-0: can't use DMA &lt;BR /&gt;i2c i2c-0: can't use DMA &lt;BR /&gt;i2c i2c-1: IMX I2C adapter registered &lt;BR /&gt;i2c i2c-1: IMX I2C adapter registered &lt;BR /&gt;i2c i2c-1: can't use DMA &lt;BR /&gt;i2c i2c-1: can't use DMA &lt;BR /&gt;pps_core: LinuxPPS API ver. 1 registered &lt;BR /&gt;pps_core: LinuxPPS API ver. 1 registered &lt;BR /&gt;pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti &amp;lt;giometti@l&lt;BR /&gt;inux.it&amp;gt; &lt;BR /&gt;pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti &amp;lt;giometti@l&lt;BR /&gt;inux.it&amp;gt; &lt;BR /&gt;PTP clock support registered &lt;BR /&gt;PTP clock support registered &lt;BR /&gt;fsl-ifc 1530000.ifc: Freescale Integrated Flash Controller &lt;BR /&gt;fsl-ifc 1530000.ifc: Freescale Integrated Flash Controller &lt;BR /&gt;fsl-ifc 1530000.ifc: IFC version 1.4, 8 banks &lt;BR /&gt;fsl-ifc 1530000.ifc: IFC version 1.4, 8 banks &lt;BR /&gt;Advanced Linux Sound Architecture Driver Initialized. &lt;BR /&gt;Advanced Linux Sound Architecture Driver Initialized. &lt;BR /&gt;Switched to clocksource arch_sys_counter &lt;BR /&gt;Switched to clocksource arch_sys_counter &lt;BR /&gt;NET: Registered protocol family 2 &lt;BR /&gt;NET: Registered protocol family 2 &lt;BR /&gt;TCP established hash table entries: 16384 (order: 4, 65536 bytes) &lt;BR /&gt;TCP established hash table entries: 16384 (order: 4, 65536 bytes) &lt;BR /&gt;TCP bind hash table entries: 16384 (order: 5, 131072 bytes) &lt;BR /&gt;TCP bind hash table entries: 16384 (order: 5, 131072 bytes) &lt;BR /&gt;TCP: Hash tables configured (established 16384 bind 16384) &lt;BR /&gt;TCP: Hash tables configured (established 16384 bind 16384) &lt;BR /&gt;UDP hash table entries: 1024 (order: 3, 32768 bytes) &lt;BR /&gt;UDP hash table entries: 1024 (order: 3, 32768 bytes) &lt;BR /&gt;UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes) &lt;BR /&gt;UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes) &lt;BR /&gt;NET: Registered protocol family 1 &lt;BR /&gt;NET: Registered protocol family 1 &lt;BR /&gt;RPC: Registered named UNIX socket transport module. &lt;BR /&gt;RPC: Registered named UNIX socket transport module. &lt;BR /&gt;RPC: Registered udp transport module. &lt;BR /&gt;RPC: Registered udp transport module. &lt;BR /&gt;RPC: Registered tcp transport module. &lt;BR /&gt;RPC: Registered tcp transport module. &lt;BR /&gt;RPC: Registered tcp NFSv4.1 backchannel transport module. &lt;BR /&gt;RPC: Registered tcp NFSv4.1 backchannel transport module. &lt;BR /&gt;Trying to unpack rootfs image as initramfs... &lt;BR /&gt;Trying to unpack rootfs image as initramfs... &lt;BR /&gt;rootfs image is not initramfs (no cpio magic); looks like an initrd &lt;BR /&gt;rootfs image is not initramfs (no cpio magic); looks like an initrd &lt;BR /&gt;Freeing initrd memory: 22488K (88000000 - 895f6000) &lt;BR /&gt;Freeing initrd memory: 22488K (88000000 - 895f6000) &lt;BR /&gt;kvm [1]: interrupt-controller@1404000 IRQ22 &lt;BR /&gt;kvm [1]: interrupt-controller@1404000 IRQ22 &lt;BR /&gt;kvm [1]: timer IRQ18 &lt;BR /&gt;kvm [1]: timer IRQ18 &lt;BR /&gt;kvm [1]: Hyp mode initialized successfully &lt;BR /&gt;kvm [1]: Hyp mode initialized successfully &lt;BR /&gt;CPU PMU: Failed to parse /pmu/interrupt-affinity[0] &lt;BR /&gt;CPU PMU: Failed to parse /pmu/interrupt-affinity[0] &lt;BR /&gt;hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available &lt;BR /&gt;hw perfevents: enabled with armv7_cortex_a7 PMU driver, 5 counters available &lt;BR /&gt;futex hash table entries: 512 (order: 3, 32768 bytes) &lt;BR /&gt;futex hash table entries: 512 (order: 3, 32768 bytes) &lt;BR /&gt;HugeTLB registered 2 MB page size, pre-allocated 0 pages &lt;BR /&gt;HugeTLB registered 2 MB page size, pre-allocated 0 pages &lt;BR /&gt;NFS: Registering the id_resolver key type &lt;BR /&gt;NFS: Registering the id_resolver key type &lt;BR /&gt;Key type id_resolver registered &lt;BR /&gt;Key type id_resolver registered &lt;BR /&gt;Key type id_legacy registered &lt;BR /&gt;Key type id_legacy registered &lt;BR /&gt;jffs2: version 2.2. (NAND) 漏 2001-2006 Red Hat, Inc. &lt;BR /&gt;jffs2: version 2.2. (NAND) 漏 2001-2006 Red Hat, Inc. &lt;BR /&gt;bounce: pool size: 64 pages &lt;BR /&gt;bounce: pool size: 64 pages &lt;BR /&gt;io scheduler noop registered &lt;BR /&gt;io scheduler noop registered &lt;BR /&gt;io scheduler deadline registered &lt;BR /&gt;io scheduler deadline registered &lt;BR /&gt;io scheduler cfq registered (default) &lt;BR /&gt;io scheduler cfq registered (default) &lt;BR /&gt;ls-scfg-msi soc:msi-controller: ibs_shift:3 msir_irqs:32 msir_base:0x4 &lt;BR /&gt;ls-scfg-msi soc:msi-controller: ibs_shift:3 msir_irqs:32 msir_base:0x4 &lt;BR /&gt;Find msi-controller /soc/msi-controller &lt;BR /&gt;Find msi-controller /soc/msi-controller &lt;BR /&gt;PCI host bridge /soc/pcie@3400000 ranges: &lt;BR /&gt;PCI host bridge /soc/pcie@3400000 ranges: &lt;BR /&gt; IO 0x4000010000..0x400001ffff -&amp;gt; 0x00000000 &lt;BR /&gt; IO 0x4000010000..0x400001ffff -&amp;gt; 0x00000000 &lt;BR /&gt; MEM 0x4040000000..0x407fffffff -&amp;gt; 0x40000000 &lt;BR /&gt; MEM 0x4040000000..0x407fffffff -&amp;gt; 0x40000000 &lt;BR /&gt;layerscape-pcie 3400000.pcie: PCI host bridge to bus 0000:00 &lt;BR /&gt;layerscape-pcie 3400000.pcie: PCI host bridge to bus 0000:00 &lt;BR /&gt;pci_bus 0000:00: root bus resource [bus 00-ff] &lt;BR /&gt;pci_bus 0000:00: root bus resource [bus 00-ff] &lt;BR /&gt;pci_bus 0000:00: root bus resource [io 0x0000-0xffff] &lt;BR /&gt;pci_bus 0000:00: root bus resource [io 0x0000-0xffff] &lt;BR /&gt;pci_bus 0000:00: root bus resource [mem 0x4040000000-0x407fffffff] (bus address &lt;BR /&gt;[0x40000000-0x7fffffff]) &lt;BR /&gt;pci_bus 0000:00: root bus resource [mem 0x4040000000-0x407fffffff] (bus address &lt;BR /&gt;[0x40000000-0x7fffffff]) &lt;BR /&gt;PCI: bus0: Fast back to back transfers disabled &lt;BR /&gt;PCI: bus0: Fast back to back transfers disabled &lt;BR /&gt;PCI: bus1: Fast back to back transfers enabled &lt;BR /&gt;PCI: bus1: Fast back to back transfers enabled &lt;BR /&gt;pci 0000:00:00.0: BAR 6: assigned [mem 0x4040000000-0x40400007ff pref] &lt;BR /&gt;pci 0000:00:00.0: BAR 6: assigned [mem 0x4040000000-0x40400007ff pref] &lt;BR /&gt;pci 0000:00:00.0: PCI bridge to [bus 01] &lt;BR /&gt;pci 0000:00:00.0: PCI bridge to [bus 01]&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Feb 2018 01:54:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/ls1021a-pcie/m-p/719560#M2976</guid>
      <dc:creator>shunpinglin</dc:creator>
      <dc:date>2018-02-06T01:54:21Z</dc:date>
    </item>
    <item>
      <title>Re: ls1021a pcie</title>
      <link>https://community.nxp.com/t5/Layerscape/ls1021a-pcie/m-p/719561#M2977</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A _jive_internal="true" data-content-finding="Community" data-userid="304303" data-username="shunpinglin" href="https://community.nxp.com/people/shunpinglin"&gt;shunping lin&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Did you use the default PCIe controller definition in arch/arm/boot/dts/ls1021a.dtsi provided in Linux SDK?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; pcie@3400000 {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reg = &amp;lt;0x00 0x03400000 0x0 0x00010000&amp;nbsp;&amp;nbsp; /* controller registers */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x40 0x00000000 0x0 0x00002000&amp;gt;; /* configuration space */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reg-names = "regs", "config";&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupts = &amp;lt;GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH&amp;gt;; /* aer interrupt */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupt-names = "pme", "aer";&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; fsl,pcie-scfg = &amp;lt;&amp;amp;scfg 0&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; #address-cells = &amp;lt;3&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; #size-cells = &amp;lt;2&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; device_type = "pci";&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; num-lanes = &amp;lt;4&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; bus-range = &amp;lt;0x0 0xff&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ranges = &amp;lt;0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000&amp;nbsp;&amp;nbsp; /* downstream I/O */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000&amp;gt;; /* non-prefetchable memory */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; msi-parent = &amp;lt;&amp;amp;msi&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; #interrupt-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupt-map-mask = &amp;lt;0 0 0 7&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupt-map = &amp;lt;0000 0 0 1 &amp;amp;gic GIC_SPI 91&amp;nbsp; IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;0000 0 0 2 &amp;amp;gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;0000 0 0 3 &amp;amp;gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;0000 0 0 4 &amp;amp;gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; pcie@3500000 {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reg = &amp;lt;0x00 0x03500000 0x0 0x00010000&amp;nbsp;&amp;nbsp; /* controller registers */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x48 0x00000000 0x0 0x00002000&amp;gt;; /* configuration space */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reg-names = "regs", "config";&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupts = &amp;lt;GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH&amp;gt;; /* aer interrupt */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupt-names = "pme", "aer";&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; fsl,pcie-scfg = &amp;lt;&amp;amp;scfg 1&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; #address-cells = &amp;lt;3&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; #size-cells = &amp;lt;2&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; device_type = "pci";&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; num-lanes = &amp;lt;4&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; bus-range = &amp;lt;0x0 0xff&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ranges = &amp;lt;0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000&amp;nbsp;&amp;nbsp; /* downstream I/O */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000&amp;gt;; /* non-prefetchable memory */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; msi-parent = &amp;lt;&amp;amp;msi&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; #interrupt-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupt-map-mask = &amp;lt;0 0 0 7&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupt-map = &amp;lt;0000 0 0 1 &amp;amp;gic GIC_SPI 92&amp;nbsp; IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;0000 0 0 2 &amp;amp;gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;0000 0 0 3 &amp;amp;gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;0000 0 0 4 &amp;amp;gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please enter into u-boot to check the PCIe device information.&lt;/P&gt;&lt;P&gt;=&amp;gt; pci read 00:00:00&lt;BR /&gt;Scanning PCI devices on bus 0&lt;BR /&gt;BusDevFun&amp;nbsp; VendorId&amp;nbsp;&amp;nbsp; DeviceId&amp;nbsp;&amp;nbsp; Device Class&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Sub-Class&lt;BR /&gt;_____________________________________________________________&lt;BR /&gt;00.00.00&amp;nbsp;&amp;nbsp; 0x1957&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0e0a&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Bridge device&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x04&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;=&amp;gt; pci header 00:00:00&lt;BR /&gt;&amp;nbsp; vendor ID =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x1957&lt;BR /&gt;&amp;nbsp; device ID =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0e0a&lt;BR /&gt;&amp;nbsp; command register ID =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0007&lt;BR /&gt;&amp;nbsp; status register =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0010&lt;BR /&gt;&amp;nbsp; revision ID =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x20&lt;BR /&gt;&amp;nbsp; class code =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x06 (Bridge device)&lt;BR /&gt;&amp;nbsp; sub class code =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x04&lt;BR /&gt;&amp;nbsp; programming interface =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00&lt;BR /&gt;&amp;nbsp; cache line =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x08&lt;BR /&gt;&amp;nbsp; latency time =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00&lt;BR /&gt;&amp;nbsp; header type =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x01&lt;BR /&gt;&amp;nbsp; BIST =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00&lt;BR /&gt;&amp;nbsp; base address 0 =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xff00000f&lt;BR /&gt;&amp;nbsp; base address 1 =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xfc00000f&lt;BR /&gt;&amp;nbsp; primary bus number =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00&lt;BR /&gt;&amp;nbsp; secondary bus number =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x01&lt;BR /&gt;&amp;nbsp; subordinate bus number =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x01&lt;BR /&gt;&amp;nbsp; secondary latency timer =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00&lt;BR /&gt;&amp;nbsp; IO base =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x10&lt;BR /&gt;&amp;nbsp; IO limit =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x10&lt;BR /&gt;&amp;nbsp; secondary status =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0000&lt;BR /&gt;&amp;nbsp; memory base =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0900&lt;BR /&gt;&amp;nbsp; memory limit =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0900&lt;BR /&gt;&amp;nbsp; prefetch memory base =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x1000&lt;BR /&gt;&amp;nbsp; prefetch memory limit =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0000&lt;BR /&gt;&amp;nbsp; prefetch memory base upper =&amp;nbsp; 0x00000000&lt;BR /&gt;&amp;nbsp; prefetch memory limit upper = 0x00000000&lt;BR /&gt;&amp;nbsp; IO base upper 16 bits =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0000&lt;BR /&gt;&amp;nbsp; IO limit upper 16 bits =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0000&lt;BR /&gt;&amp;nbsp; expansion ROM base address =&amp;nbsp; 0x08000000&lt;BR /&gt;&amp;nbsp; interrupt line =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xff&lt;BR /&gt;&amp;nbsp; interrupt pin =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x01&lt;BR /&gt;&amp;nbsp; bridge control =&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x0000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In addition, did you use Linux SDK 2.0 1703?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;TIC&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 11 Feb 2018 06:12:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/ls1021a-pcie/m-p/719561#M2977</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2018-02-11T06:12:31Z</dc:date>
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