How to resolve Synchronous Abort handler issue for PCIe PEX4?

meenachik — Thu, 31 Aug 2017 06:59:35 GMT

Hi all,

The PCIe PEX4 bus enumeration problem for LS2088A board.I have Configured PEX2/PEX4 as RC and PEX3 as EP.
The PEX2 is configured as RC & PEX3 as EP while booting.The PEX4 bus enumeration produces the Synchronous Abort issue.

U-Boot Log:

U-Boot 2016.01LS2088A-SDK+g8870d3a (Aug 01 2017 - 20:31:06 +0530)

SoC: LS2088E Version:1.0 (0x87090010)
Clock Configuration:
CPU0(A72):1600 MHz CPU1(A72):1600 MHz CPU2(A72):1600 MHz
CPU3(A72):1600 MHz CPU4(A72):1600 MHz CPU5(A72):1600 MHz
CPU6(A72):1600 MHz CPU7(A72):1600 MHz
Bus: 600 MHz DDR: 1333.333 MT/s DP-DDR: 1333.333 MT/s
Reset Configuration Word (RCW):
00000000: 40282830 40400040 00000000 00000000
00000010: 00000000 00000000 00200000 00000000
00000020: 0b212980 00002580 00000000 00000000
00000030: 00000a08 00000000 00000000 00000080
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00027000 00000000
00000070: 51350000 00000000 00000000 00000000
I2C: ready
Model: Freescale Layerscape 2088a ISSD Board
Board: LS2085A/LS2088A-QDS, Board Arch: V1, Board Version: A
CPLD_NIC Version: A10
DRAM: Initializing DDR....using SPD
Detected UDIMM 9965657-004.A00G
Detected UDIMM 9965657-004.A00G
Address hashing enabled.
Address hashing enabled.
15 GiB
DDR 15 GiB (DDR4, 64-bit, CL=9, ECC on)
DDR Controller Interleaving Mode: 256B
DDR Chip-Select Interleaving Mode: CS0+CS1
fsl-ppa: Bad firmware image (not a FIT image)
fsl-ppa: error (-22)
fsl-ppa: Bad firmware image (not a FIT image)
Waking secondary cores to start from fff14000
All (8) cores are up.
Using SERDES1 Protocol: 53 (0x35)
Using SERDES2 Protocol: 81 (0x51)
Flash: 128 MiB
MMC: FSL_SDHC: 0
EEPROM: NXID v1
PCIe1: disabled
PCIe2: Root Complex x4 gen2, regs @ 0x3500000
PCI:
01:00.0 - 1957:0953 - Mass storage controller

PCIe2: Bus 00 - 01
PCIe3: Endpoint x4 gen1, regs @ 0x3600000
PCIe4: Root Complex x4 gen2, regs @ 0x3700000
PCI:
"Synchronous Abort" handler, esr 0x96000005
ELR: fff56300
LR: fff56278
x0 : 0000003800000000 x1 : 0000000001000000
x2 : 000000380000000c x3 : 0000000000000003
x4 : 0000000000000003 x5 : 0000000000000000
x6 : 0000000000000000 x7 : 0000000000000000
x8 : 0000000000000190 x9 : 000000000000000c
x10: 00000000000003ff x11: 0000000000000000
x12: 0000000000000001 x13: 0000000040000000
x14: 0000000000200000 x15: 0000000000000001
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000ffd0fd88 x19: 000000000000000c
x20: 00000000ffd10a40 x21: 0000000000000003
x22: 0000000000030000 x23: 00000000ffd0e1ec
x24: 00000000fff88da6 x25: 000000000003ff00
x26: 00000000fffbbc90 x27: 00000000fff89200
x28: 0000000000000000 x29: 00000000ffd0e180

Resetting CPU ...

### ERROR ### Please RESET the board ###

I have tried to trace the issue in u-boot source code

Workaround:
1. When pci_bus scannning process in u-boot,it tries to read the pcie_header_type abort occur.

PEX2 also configured as RC but it get bus enumeration correctly and PEX4 only arise this issue.

2. Disble the pcie_setup_ctrl in RC u-boot. PEX4 abort not arise.but PCIe both bus gets enumerated wrongly.In kernel ,PCI rescan is required to detected the device.

I do know the exact reason for this issue.If any one know about this.Please,help me to resolve this issue.

Thanks,
Meenachi

topic How to resolve Synchronous Abort handler issue for PCIe PEX4? in Layerscape

How to resolve Synchronous Abort handler issue for PCIe PEX4?