<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LayerscapeのトピックRe: LS1021A GPIO usage peculiarity</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1021A-GPIO-usage-peculiarity/m-p/699956#M2785</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Having created&amp;nbsp;a Service Request on this issue, I've obtained&amp;nbsp;two responses:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;EM&gt;Mentioned threads can be interpreted in a way that it is not possible to use partial GPIO3 ports, all should be used.&lt;BR /&gt;&lt;/EM&gt;&lt;EM&gt;This is wrong conclusion, and statement from the community "You don't have an option to only select subset of the GPIO3 pins." is also wrong.&lt;/EM&gt;&lt;/LI&gt;&lt;LI&gt;&lt;EM style="background-color: #ffffff; color: #51626f;"&gt;Information provided in the thread #365969 is out of date.&lt;/EM&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 28 Aug 2017 07:49:00 GMT</pubDate>
    <dc:creator>fdm</dc:creator>
    <dc:date>2017-08-28T07:49:00Z</dc:date>
    <item>
      <title>LS1021A GPIO usage peculiarity</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1021A-GPIO-usage-peculiarity/m-p/699954#M2783</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/thread/365969#comment-570991"&gt;There is some information&lt;/A&gt; concerning GPIO pins usage in LS1021A:&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;&lt;EM&gt;Based on feedback from SW/design team If we want use all the GPIO3, we should set all the GPIO3 pin by RCW.&lt;/EM&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;EM&gt;Include: EC1,EC2,EC3 and MDC_MDIO. You don't have option to only select subset of the GPIO3 pins. This is applicable to all GPIO ports.&lt;/EM&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;EM&gt;416-418 EC1 = 001 GPIO3[2:14]&lt;/EM&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;EM&gt;419-421 EC2 =001 GPIO3[15:27]&lt;/EM&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;EM&gt;422-424 EC3 =001 GPIO3[28:31]&lt;/EM&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;EM&gt;425-426 MDC_MDIO =01 GPIO3[0:1]&lt;/EM&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;EM&gt;Unfortunately this information not explained in the RM.&lt;/EM&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;I am not sure&amp;nbsp;if I understand this&amp;nbsp;right.&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;Is it&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;mandatory&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;to set&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;all 4 groups&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;of&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;GPIO3&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;related RCW bits to the "GPIO" state in order to use&amp;nbsp;only&amp;nbsp;two GPIO3 pins (&lt;SPAN style="background-color: #ffffff;"&gt;GPIO3_13 and GPIO3_14&lt;/SPAN&gt; in that use case), thus making e.g. eTSEC3 RGMII interface unusable?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;In contrast with the foregoing, one of our custom LS1021A based boards successfully uses SDHC interface and&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN&gt;GPIO2_24&amp;nbsp;&lt;/SPAN&gt;pin as GPIO output&amp;nbsp;simultaneously despite&amp;nbsp;of the fact that&amp;nbsp;GPIO2[4:9] pins are&amp;nbsp;shared with SDHC.&lt;/P&gt;&lt;DIV class=""&gt;&lt;DIV&gt;&lt;FORM enctype="application/x-www-form-urlencoded" name="text_form"&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt; &lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/FORM&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;As far as I know, this fact is not documented so far.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Is there any additional background info on this issue?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;BR,&lt;/SPAN&gt;&lt;BR style="color: #51626f; background-color: #ffffff;" /&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp; &amp;nbsp;Denis&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 16 Aug 2017 16:05:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1021A-GPIO-usage-peculiarity/m-p/699954#M2783</guid>
      <dc:creator>fdm</dc:creator>
      <dc:date>2017-08-16T16:05:36Z</dc:date>
    </item>
    <item>
      <title>Re: LS1021A GPIO usage peculiarity</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1021A-GPIO-usage-peculiarity/m-p/699955#M2784</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;/P&gt;&lt;P&gt;It is supposed that each GPIO RCW field controls only own group of GPIOn pins. You could see that for the GPIO2 pins. But according to &lt;A _jive_internal="true" href="https://community.nxp.com/thread/365969#comment-570991"&gt;https://community.nxp.com/thread/365969#comment-570991&lt;/A&gt; there is hardware issue for&amp;nbsp; the GPIO3 pins. As result all these 4 fields should be set for GPIO3 even for one group using.&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 Aug 2017 13:29:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1021A-GPIO-usage-peculiarity/m-p/699955#M2784</guid>
      <dc:creator>r8070z</dc:creator>
      <dc:date>2017-08-17T13:29:18Z</dc:date>
    </item>
    <item>
      <title>Re: LS1021A GPIO usage peculiarity</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1021A-GPIO-usage-peculiarity/m-p/699956#M2785</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Having created&amp;nbsp;a Service Request on this issue, I've obtained&amp;nbsp;two responses:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;EM&gt;Mentioned threads can be interpreted in a way that it is not possible to use partial GPIO3 ports, all should be used.&lt;BR /&gt;&lt;/EM&gt;&lt;EM&gt;This is wrong conclusion, and statement from the community "You don't have an option to only select subset of the GPIO3 pins." is also wrong.&lt;/EM&gt;&lt;/LI&gt;&lt;LI&gt;&lt;EM style="background-color: #ffffff; color: #51626f;"&gt;Information provided in the thread #365969 is out of date.&lt;/EM&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Aug 2017 07:49:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1021A-GPIO-usage-peculiarity/m-p/699956#M2785</guid>
      <dc:creator>fdm</dc:creator>
      <dc:date>2017-08-28T07:49:00Z</dc:date>
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  </channel>
</rss>

