Layerscape中的主题 Re: What are USB1/2/3_DRVVBUS rule?

What are USB1/2/3_DRVVBUS rule?

upartners — Fri, 19 May 2017 08:09:45 GMT

We design our product refer to the LS1043ARDB. On the basis of MiniPCIE circuit diagramand, if using the USB3 as host mode, we must add circuit to tie the USB3_ID to GND. As I know, the USB3_VBUS and USB2_VBUS share power USB2_P2_PWR which is controlled by USB2_DRVVBUS Pin.

Could you please explain what are USB1/2/3_DRVVBUS rule?

The USB3_DRVVBUS Pin is used for TDMA_RQ in the LS1043ARDB, we use USB3 as host mode, deos USB3_DRVVBUS need? We want to use USB2 and USB3 independently.

The USB2_DRVVBUS is a multi-functional pin( 000 IIC3_SCL, 001 GPIO_4[10], 010 EVT_B[5], 011 USB2_DRVVBUS,100 BRGO4,101 FTM8_CH0,110 CLK11), the default value is 0x0 on HRESET，It is means that the default function is IIC3_SCL. In the SDK code, I can not find where does configure this pin function? Could you please help me? If, I will be very grateful.

Looking forward to your reply.

Have a great day.

Re: What are USB1/2/3_DRVVBUS rule?

Pavel — Mon, 22 May 2017 01:53:54 GMT

The USB2_DRVVBUS and USB3_DRVVBUS are output of the LS1043a USB controllers. These pins are used for enable USB_VBUS using external power switch like to MX1558.

The USBn_PWRFAULT are input indicates that a Vbus fault has occurred. Power switch set low on this pin if a Vbus fault has occurred.

If the LS1043a is USB host, these signals are needed for providing USB VBUS.

Have a great day,
Pavel Chubakov

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Re: What are USB1/2/3_DRVVBUS rule?

upartners — Mon, 22 May 2017 02:30:38 GMT

Thanks a lot.

On LS1043ARDB,the USB3_VBUS share the power USB2_P2_PWR which is controlled by USB2_DRVVBUS with USB2_VBUS . My question is if we use USB3 as USB 2.0 HOST mode,can the USB3_VBUS share the power USB2_P2 PWR with USB2_VBUS? USB3 and USB2 work independently,sometimes the USB3 work and USB2 didn't work.

The USB2_DRVVBUS is a multi-functional pin( 000 IIC3_SCL, 001 GPIO_4[10], 010 EVT_B[5], 011 USB2_DRVVBUS,100 BRGO4,101 FTM8_CH0,110 CLK11), the default value is 0x0 on HRESET，It is means that the default function is IIC3_SCL. In the SDK code, I can not find WHERE does configure this pin function? How can we configure this pin to USB2/3_DRVVBUS fuction? and how can we control the USB1/2/3_DRVVBUS output as high or low? Could you please help me? If, I will be very grateful.

Looking forward to your reply.

Have a great day.

Re: What are USB1/2/3_DRVVBUS rule?

upartners — Fri, 26 May 2017 09:38:06 GMT

Hi nxp,

Can someone help me?

Re: What are USB1/2/3_DRVVBUS rule?

Pavel — Fri, 26 May 2017 11:00:51 GMT

Look at the LS1043a RCW bits 429 and 430.

See also the SCFG_RCWPMUXCR0, SCFG_USBDRVVBUS_SELCR, SCFG_USBPWRFAULT_SELCR and DCFG_CCSR_DEVDISR1 registers of the LS1043a.

Have a great day,
Pavel Chubakov

Re: What are USB1/2/3_DRVVBUS rule?

upartners — Sat, 27 May 2017 08:30:56 GMT

Thanks a lot.

I know that I can config the RCW.
The trouble I encountered was that I could not find the configuration source code in the SDK and where coulde I add the configure code,uboot or pbi? I think the LS1043ARDB config the pin L4 as USB2_DRVVBUS function, but I have great difficulty finding the configure code.

More importantly, I am hard to master how can we control the USB1/2/3_DRVVBUS output as high or low to enable/disable the USB_VBUS?Are they automatically controlled by USB module, or manually controlled by configure code?Could you please help me?