Second Core startup address

dainiuszilys — Mon, 03 Jul 2017 19:05:07 GMT

I'm going to run dual-core LS1020A. Core 0 startsup from the location, written into SCRATCHRW1 - that's fine. But what about core 1 startup location after releasing it? Will it jump to the same location?

I didn't find it documented.

Re: Second Core startup address

Pavel — Wed, 05 Jul 2017 07:08:53 GMT

The LS1021a Core 0 is enabled using the RCW[BOOT_HO] bit.

The LS1021a Core 0 uses software for setting the Boot Location Pointer for core 1 via the SCRATCHRW1 register and enabling Core 1 using the DCFG_CCSR_BRR register.

See the following pages:

https://lists.denx.de/pipermail/u-boot/2014-November/196577.html

https://gitlab.labs.nic.cz/turris/u-boot-turris/blob/b724bd7d63498449d3960bbd3075ba94d7152890/arch/arm/cpu/armv7/ls102xa/cpu.c

Have a great day,
Pavel Chubakov

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Second Core startup address

Re: Second Core startup address