Layerscape中的主题 How to keep cache coherency between DPAA and Ctx-A53 on LS1043A

How to keep cache coherency between DPAA and Ctx-A53 on LS1043A

uncoldice — Fri, 02 Jun 2017 05:03:11 GMT

Hi,

I am trying to use DPAA to transmit ethernet packet on LS1043ARDB board.

I use cache-enabled memory to encapsulate the ethernet packet data. When doing the qman portal enqueue operation, I have to flush the cache of this memory in order that DPAA can get proper data.

My question is: to avoid the load introduced by cache flush, is there an implement of the cache coherency between DPAA and ARM core in hardware?

Thanks.

Re: How to keep cache coherency between DPAA and Ctx-A53 on LS1043A

bpe — Wed, 07 Jun 2017 10:09:16 GMT

FMAN DMA always issues snoopable transactions for buffers. If you are working with Linux SDK, make sure you did

not alter the kernel configuration to disable CCI-400 and SMMU support. If you are working in a non-Linux environment,

check Linux kernel source code, files arm-cci.c and arch/arm64/mm/dma-mapping.c (links below) for the corresponding attributes setting procedures:

http://git.freescale.com/git/cgit.cgi/ppc/sdk/linux.git/tree/drivers/bus/arm-cci.c?id=fsl-sdk-v2.0-1703
http://git.freescale.com/git/cgit.cgi/ppc/sdk/linux.git/tree/arch/arm64/mm/dma-mapping.c?id=fsl-sdk-v2.0-1703

Have a great day,
Platon

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Re: How to keep cache coherency between DPAA and Ctx-A53 on LS1043A

uncoldice — Mon, 12 Jun 2017 07:04:45 GMT

Hi,

I have a new question about the CCI-400.

In LS1043ARM.pdf chapter 9.1.3, for the BMAN/QMAN/FMAN snoop transaction configuration, it says "Refer LS1043ADPAARM for more details". However, I cannot find any related information from LS1043ADPAARM Rev.0 04/2016.

Is there any updated DPAARM that contains this configuration? If yes, please share the way to get it.

Thank you.