topic DDR4-1600 errata clarification on LS1043 in Layerscape https://community.nxp.com/t5/Layerscape/DDR4-1600-errata-clarification-on-LS1043/m-p/669308#M2485 <HTML><HEAD></HEAD><BODY><P>The LS1043 A-007864 errata says "If a DRAM data bus width of 16 bits or less is used with DDR4 memories running at 1600 MT/s data rate, then tCCD_L is violated by the controller". Does this refer to the component data width or the full width of the controller? If the latter, does this mean that tCCD_L will be five cycles when the controller data width is 32 bits?</P><P></P><P>We have two 16-bit components combined to a 32-bit memory and we are experiencing memory corruption at 1600 MT/s. Things appear to work at 1333 MT/s.</P></BODY></HTML> Wed, 31 May 2017 08:55:32 GMT perchrc 2017-05-31T08:55:32Z DDR4-1600 errata clarification on LS1043 https://community.nxp.com/t5/Layerscape/DDR4-1600-errata-clarification-on-LS1043/m-p/669308#M2485 <HTML><HEAD></HEAD><BODY><P>The LS1043 A-007864 errata says "If a DRAM data bus width of 16 bits or less is used with DDR4 memories running at 1600 MT/s data rate, then tCCD_L is violated by the controller". Does this refer to the component data width or the full width of the controller? If the latter, does this mean that tCCD_L will be five cycles when the controller data width is 32 bits?</P><P></P><P>We have two 16-bit components combined to a 32-bit memory and we are experiencing memory corruption at 1600 MT/s. Things appear to work at 1333 MT/s.</P></BODY></HTML> Wed, 31 May 2017 08:55:32 GMT https://community.nxp.com/t5/Layerscape/DDR4-1600-errata-clarification-on-LS1043/m-p/669308#M2485 perchrc 2017-05-31T08:55:32Z Re: DDR4-1600 errata clarification on LS1043 https://community.nxp.com/t5/Layerscape/DDR4-1600-errata-clarification-on-LS1043/m-p/669309#M2486 <HTML><HEAD></HEAD><BODY><P>The errata refers to DDR bus width of the controller.</P><P>What kind of corruptions in your case? Did you check ERR_DETECT register after DDR initialization for errors?</P><P></P><P>Regards,</P><P>Bulat</P></BODY></HTML> Thu, 01 Jun 2017 10:51:01 GMT https://community.nxp.com/t5/Layerscape/DDR4-1600-errata-clarification-on-LS1043/m-p/669309#M2486 Bulat 2017-06-01T10:51:01Z