PMU Cache counters

renatosala — Wed, 15 Mar 2017 17:48:08 GMT

We are doing performance measurement on a LS1043A Processor using the PMU counters. We notice something that seems strange. A simple program (that runs without any operating system) contains a loop that reads from the RAM memory locations spaced of 64 bytes, all variables ( loop counter, address to read and data ) are stored in registers. The cache is enabled. As a result we have that the L1D_CACHE_WB PMU counter has quite the same value of the MEM_ACCESS, while we expected the L1D_CACHE_WB to be quite 0 since no write-back operations should occur and, in fact the L2D_CACHE_WB is quite 0. Have you any suggestions ?

Re: PMU Cache counters

ufedor — Thu, 16 Mar 2017 03:54:46 GMT

It will be convenient to investigate the issue as Technical Case:

https://community.freescale.com/thread/381898

Please create a Case and provide detailed description of the test reproduction.

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PMU Cache counters

Re: PMU Cache counters