LayerscapeのトピックRe: eth0 (eTSEC1) On A LS1021a-TWR Board

eth0 (eTSEC1) On A LS1021a-TWR Board

tafthorne — Mon, 26 Sep 2016 14:55:43 GMT

Starting a new thread as requested by silviawang‌ when I posted on

https://community.nxp.com/message/835277?commentID=835277&et=watches.email.thread#comment-835277

My original message was:

I seem to have eth1 working happily under a recent build of the fsl community code. When I try to use eth0 and eth2 they do not seem to send or receive any packets. I must have a weird bit of config somewhere causing this.

I can use ifconfig to assign IP addresses to any interface. I can take eth1 and eth2 up and down and see messages such as (when a cable is connected):

root@ls1021atwr:/# ifconfig eth2 up
root@ls1021atwr:/# libphy: mdio@2d24000:01 - Link is Up - 1000/Full

Remove cable from eth2 and plug it into eth1

libphy: mdio@2d24000:01 - Link is Down
libphy: mdio@2d24000:00 - Link is Up - 1000/Full

Remove cable from eth1 and plug into eth0

# libphy: mdio@2d24000:00 - Link is Down
libphy: mdio@2d24000:02 - Link is Up - 1000/Full

I have checked that SW3[5] is off.

Silvia replied asking that I:

Please check whether eTSEC1, eTSEC2 and eTSEC3 can work under u-boot?

If no, please provide u-boot log including RCW.

If yes, please provide Linux Kernel git adress(commit ID), dts and Kernel configuration file.

Do you use LS1021 CPU 1.0 or 2.0?

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

tafthorne — Mon, 26 Sep 2016 15:00:35 GMT

Please check whether eTSEC1, eTSEC2 and eTSEC3 can work under u-boot?

I am not sure how best to do that. Here is my attempt, which I think shows eTSEC1 failing but eTSEC2 and eTSEC3 working.

=> mdio list
FSL_MDIO:
0 - AR8031/AR8033 <--> eTSEC2
1 - AR8031/AR8033 <--> eTSEC3
2 - AR8031/AR8033 <--> eTSEC1

=> mdio read eTSEC1 1
Reading from bus FSL_MDIO
PHY at address 2:
1 - 0x7949
=> mdio read eTSEC2 1
Reading from bus FSL_MDIO
PHY at address 0:
1 - 0x7949
=> mdio read eTSEC3 1 
Reading from bus FSL_MDIO
PHY at address 1:
1 - 0x796d

=> ping 192.168.0.10
Speed: 1000, full duplex
Using eTSEC3 device
host 192.168.0.10 is alive
=> setend ethact eTSEC2
Unknown command 'setend' - try 'help'
=> setenv ethact eTSEC2
=> ping 192.168.0.10 
eTSEC2 Waiting for PHY auto negotiation to complete......... TIMEOUT !
eTSEC2: No link.
Speed: 1000, full duplex
Using eTSEC3 device
host 192.168.0.10 is alive
=> 
eTSEC3 Waiting for PHY auto negotiation to complete......... TIMEOUT !
eTSEC3: No link.
eTSEC1 Waiting for PHY auto negotiation to complete......... TIMEOUT !
eTSEC1: No link.
Speed: 1000, full duplex
Using eTSEC2 device
host 192.168.0.10 is alive
=> 
Speed: 1000, full duplex
Using eTSEC2 device
host 192.168.0.10 is alive
=> 
Speed: 1000, full duplex
Using eTSEC2 device
host 192.168.0.10 is alive
=> ping 192.168.0.10
Speed: 1000, full duplex
Using eTSEC2 device
host 192.168.0.10 is alive
=> setenv ethact eTSEC1
=> 
=> 
=> ping 192.168.0.10 
eTSEC1 Waiting for PHY auto negotiation to complete......... TIMEOUT !
eTSEC1: No link.
Speed: 1000, full duplex
Using eTSEC2 device
host 192.168.0.10 is alive
=> 
eTSEC2 Waiting for PHY auto negotiation to complete......... TIMEOUT !
eTSEC2: No link.
eTSEC3 Waiting for PHY auto negotiation to complete......... TIMEOUT !
eTSEC3: No link.
Speed: 1000, full duplex
Using eTSEC1 device
ping failed; host 192.168.0.10 is not alive
=> 
Speed: 1000, full duplex
Using eTSEC1 device
ping failed; host 192.168.0.10 is not alive
=> ping 192.168.0.10
Speed: 1000, full duplex
Using eTSEC1 device
ping failed; host 192.168.0.10 is not alive

I will work on the U-Boot log and RCW post next.

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

tafthorne — Mon, 26 Sep 2016 15:02:52 GMT

If no, please provide u-boot log including RCW.

Here is the output from U-Boot from power on up until the "Hit any key to stop autoboot: " message.

U-Boot 2015.01+ls1+g3281947 (Jul 30 2015 - 20:01:52)

CPU: Freescale LayerScape LS1021E, Version: 2.0, (0x87081120)
Clock Configuration:
 CPU0(ARMV7):1000 MHz, 
 Bus:300 MHz, DDR:800 MHz (1600 MT/s data rate), 
Reset Configuration Word (RCW):
 00000000: 0608000a 00000000 00000000 00000000
 00000010: 70000000 00007900 e0025a00 21046000
 00000020: 00000000 00000000 00000000 20000000
 00000030: 00080000 881b7340 00000000 00000000
Board: LS1021ATWR
CPLD: V2.0
PCBA: V1.0
VBank: 0
I2C: ready
DRAM: 1 GiB
Using SERDES1 Protocol: 112 (0x70)
Firmware 'Microcode version 0.0.1 for LS1021a r1.0' for 1021 V1.0
QE: uploading microcode 'Microcode for LS1021a r1.0' version 0.0.1
Flash: 128 MiB
MMC: FSL_SDHC: 0
EEPROM: NXID v1
PCIe1: Root Complex no link, regs @ 0x3400000
PCIe2: Root Complex no link, regs @ 0x3500000
In: serial
Out: serial
Err: serial
SEC0: RNG instantiated
SATA link 0 timeout.
AHCI 0001.0300 1 slots 1 ports ? Gbps 0x1 impl SATA mode
flags: 64bit ncq pm clo only pmp fbss pio slum part ccc 
scanning bus for devices...
Found 0 device(s).
SCSI: Net: eTSEC2 is in sgmii mode.
eTSEC1, eTSEC2, eTSEC3 [PRIME]
Hit any key to stop autoboot: 0 
=>

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

tafthorne — Mon, 26 Sep 2016 15:16:40 GMT

If yes, please provide Linux Kernel git address(commit ID), dts and Kernel configuration file.

Well the Kernel git commit ID is probably given here:

## Booting kernel from Legacy Image at 82000000 ...
 Image Name: Linux-3.12.37-rt51+ls1+gf488de6
 Image Type: ARM Linux Kernel Image (uncompressed)
 Data Size: 3081864 Bytes = 2.9 MiB
 Load Address: 80008000
 Entry Point: 80008000
 Verifying Checksum ... OK
## Flattened Device Tree blob at 8f000000
 Booting using the fdt blob at 0x8f000000
 Loading Kernel Image ... OK
 Loading Device Tree to bef1b000, end bef23205 ... OK

The DTS is whatever is hiding in the fsl community edition SDK. I think I found that the other day... yes I think it is under `fsl-community-bsp/build/tmp/work-shared/ls1021atwr/kernel-source/arch/arm/boot/dts/ls1021a-twr.dts`. I shall attach that file as `ls1021a-twr.dts`.

The Kernel configuration file now were is that going to be for me... `fsl-community-bsp/sources/meta-fsl-arm/recipes-kernel/linux/linux-ls1/defconfig` looks like the right sort of path name. I shall attache that file as `linux-ls1_defconfig`.

I hope that covers everything that you requested.

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

tafthorne — Mon, 26 Sep 2016 15:19:06 GMT

I forgot to say that I moved the physical connection between each port as I tested them. If the port did not seem to work I moved the cable repeatedly until it did work or I ran out of ports to try. The

Waiting for PHY auto negotiation to complete
messages are an indication of my moving the connector to a new port.

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

yipingwang — Tue, 27 Sep 2016 11:09:46 GMT

Hello Thomas Thorne,

Please let me know whether it is possible to use Linux SDK 2.0 from Linux® SDK for QorIQ Processors|NXP .

I am afraid the u-boot is not compatible with your Linux Kernel, u-boot is too old.

The attached is SDK 1.9 u-boot, please check whether it could work with your Linux Kernel.

If your problem remains, please let me know where you got the Linux Kernel source, please provide a link to me.

Have a great day,
Yiping

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Re: eth0 (eTSEC1) On A LS1021a-TWR Board

tafthorne — Wed, 28 Sep 2016 07:21:45 GMT

> I am afraid the u-boot is not compatible with your Linux Kernel, u-boot is too old.

If that is the cause of my issue it should not be too difficult to fix. I was being a little bit lasy and continuing to use the U-Boot binary that came pre-programmed in my LS1021a-TWR board. I will try using the U-Boot binary generated as part of the SDK build I am using, or the version that you have attached above.

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

yipingwang — Wed, 28 Sep 2016 07:28:45 GMT

Hello Thomas Thorne,

Please use u-boot and Kernel from the same version SDK, according to your Kernel log information, Linux Kernel version is similar as SDK 1.9, so I provide SDK 1.9 u-boot to you, If you have u-boot binary, please try yours and let me know the result.

Have a great day,
Yiping

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

subramoniapilla — Wed, 16 Nov 2016 07:03:07 GMT

I am using 2.0 SDK and facing the same issue. Eth0 is not working, whereas eth1 and eth2 is working. Is it fixed?

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

yipingwang — Wed, 16 Nov 2016 09:29:49 GMT

Hello subramonia pillai,

Would you please create a new thread to discuss more about your problem?

Please provide your u-boot and Linux Kernel log.

Have a great day,
Yiping

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

subramoniapilla — Wed, 16 Nov 2016 09:38:19 GMT

Hi,

I am using the boot loader and kernel came along with the Board. It is 2.0

Thanks.

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

keestrommel — Wed, 16 Nov 2016 14:28:01 GMT

I had the same problem.

Strangely at new LS1021A Tower boards the SerDes protocol configuration in the RCW is 0x70 (bit 128-135 of the RCW). This protocol does not configure lane C as an SGMII1 but as PCIe2 and therefore eth0 is not working. To fix it you have to program the following RCW you can find in your SDK 2.0 installation:

QorIQ-SDK-V2.0-20160527-yocto/build_ls1021atwr/tmp/deploy/images/ls1021atwr/rcw/ls1021atwr/SSR_PNS_30/rcw_1000.bin

This will set the SerDes protocol to 0x30 with configures lane C as SGMII1.

NOR RCW program instructions:
tftp 81000000 rcw_1000.bin
erase 60000000 6001ffff
cp 81000000 60000000 $filesize

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

tae-hyungkim — Thu, 17 Nov 2016 00:38:57 GMT

This issue is very old.

I have two twr-ls1021 boards and two ls1021-iot boards.

Two board type have a same issue.

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

dusanferbas — Wed, 23 Nov 2016 01:28:08 GMT

We have several IoT boards and to follow the main stream, we also bought a Tower board. We still have a problem with ethernets, mainly eth0.
Preloaded images, that came with the board, has the wrong 0x70 SerDes config.
We made image from the Yocto and then ethernet interfaces work only the u-boot, but not from the Linux.

As previous comments pointed to a wrong RCW setting for the SGMII1 interface, they are right. But this is only the software part placing proper signals onto SerDes lines from the uP. Then these signals should be properly handled in the hardware, i.e. properly MUXed. I checked the CPLD program and I think, when you switch SW3.6 to SGMII1 position, the CPLD does not switch the MUX to SGMII1.

Please check my thoughts:

DIP SW logic is opposite than on the IoT board. On Tower, when DIP SW=ON, resulting signal is log. 1.
SW3.6 =OFF -> MUX_SEL1=0, i.e. SATA -> mux_sata_sgmii1 = 1, i.e. SGMII1a is connected (older board rev, newer boards does not have this MUX).

All other mux sel signals are set by CPLD to log. 1.
Result is lane C=MPCIE2, D=SGMII2. In other words, you have ethernet SGMII, but on PCIE2 wires.

So there is a need for a software to set the CPLD into soft mux mode and seed config into serdes_mux[1]=0.
Maybe I am wrong and in that case, I appreciate some other ideas.
If I am right, I would like to have a software patch or the CPLD patch.

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

keestrommel — Wed, 23 Nov 2016 07:44:42 GMT

With "CPLD V2.3 LS1021A SDK V1.3" I can use eTSEC1/eth0 (S3.6 = OFF).

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

dusanferbas — Wed, 23 Nov 2016 10:19:19 GMT

We bought the board 2 weeks ago from Mouser and it has CPLD V2.0 LS1021A-PB SDK V0.4 on the CPLD chip.
The SDK 0.4 is the most recent SDK available from NXP. How can I get the SDK V1.3 and the CPLD V2.3?

Can someone disclose the CPLD V2.3 source code? I have the CPLD-TWR-LS1021A-PB_V1.1.zip from probably March 2015.

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

keestrommel — Wed, 23 Nov 2016 10:44:32 GMT

I have also a TWR-LS1021A-PB board with the same CPLD version you mentioned and also on this board eth0/eTSEC1 is working fine (with a RCW with SerDes protocol 0x30). At this board S3.6 = ON.

I assume that the CPLD and SDK version numbers are reset for Rev 2 of the LS1021A (TWR-LS1021A-PB uses Rev 2). So probably Rev 2 SDK V0.4 is newer than Rev 1 SDK v1.3 and assume that the same applies for the CPLD versions Rev 2 v2.0 newer than Rev 1 v2.3).

F.Y.I the source code of Rev 1 CPLD v2.3 is from July 2014.

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

dusanferbas — Wed, 23 Nov 2016 15:43:11 GMT

Images, which arrived on SD card with the board were made for the 0x70 SerDes configuration (as can be seen from many logs here). Is it possible to make a web site, where working images can be downloaded for various configurations?

I asked tech support to do this for the IoT to have all 3 ethernets working, but they sent me images built with SDK 2.0, but they did not worked.
We were able to use images from SDK 1.8, but there the ethernet was not working properly.
Can we test your kernel?
We will not use it, just for a test, because finally we anyway need to made or own build.

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

keestrommel — Wed, 23 Nov 2016 15:55:38 GMT

In case of a NOR boot the RCW is not part of the U-Boot, it is an image on itself. You have to flash it independed of the U-Boot. The RCW image with the 0x30 SerDes protocol is part of the SDK (any version that supports the ls1021atwr). For details where to find the RCW image and how to flash it see my post of 16-Nov-2016 15:28

Re: eth0 (eTSEC1) On A LS1021a-TWR Board

dusanferbas — Thu, 24 Nov 2016 00:09:20 GMT

Are you loading the PBI from NOR and then the rest from SD card or elsewhere?

If I understand the pre-boot loader (PBL) functionality correctly, the PBL loads the PBI from a device selected with the RCW source (IFC address bus). First block of the PBI is RCW, then several registers are initialized and then first part of the u-boot is loaded as blocks of 64 bytes (max PBI block size). This is being loaded into internal static RAM within the uP. Not all of the u-boot is loaded this way, because it does not fit into internal RAM. So this part of u-boot initializes DDR RAM and loads the rest of the u-boot into it.

This means the RCW is always part of the device the uP is booting from. To reply to your comment - I think the RCW is not part of the u-boot, but the 1st part of the u-boot is part of the PBI, where the RCW also resides as its 1st block.
So if I am booting from the SD card, the uP does not use what is flashed in the NOR flash and I am fine with placing the PBI to the SD card.

If you are using the NOR for boot, I think both PBI and the rest of the u-boot should reside in the NOR flash.