https://community.nxp.com/t5/Layerscape/DDR3L-AC-DC-input-high-voltage-too-low/m-p/651228#M2257 <HTML><HEAD></HEAD><BODY><P>It is convenient to investigate the issue as Technical Case:</P><P><A href="https://community.freescale.com/thread/381898">https://community.freescale.com/thread/381898</A></P></BODY></HTML> Thu, 08 Dec 2016 06:25:51 GMT ufedor 2016-12-08T06:25:51Z https://community.nxp.com/t5/Layerscape/DDR3L-AC-DC-input-high-voltage-too-low/m-p/651227#M2256 <HTML><HEAD></HEAD><BODY><P style="margin: 0cm 0cm 0pt;">Hello,</P><P style="margin: 0cm 0cm 0pt;">we use a LS1021A (LS1021AXE7KQB) in a costumer specific Design. As DDR3L-Ram we use 1x Nanya NT5CC256M16DP-DIH with 16-bit Data bus width and 1600MT/s. The control and address lines are terminated with 39Ohm-Resistors tied to VTT (0,675V).</P><P style="margin: 0cm 0cm 0pt;">According to the DDR3-L Compliance Test App (Keysight Test-App, Signal Analyzer: DSO90604A) the High Level VIH.CA (AC) and VIH.CA(DC) at the Adress an Control Input Pins (e.g. A2) are to low (see attached). 760mV instead of 810mV minimum according to the JEDEC Standard No. 79-3-1A.01, Table 4.</P><P style="margin: 0cm 0cm 0pt;">We already tried different Termination resistors (27R and 100R) with the same result.</P><P style="margin: 0cm 0cm 0pt;">What could be the reason for this?</P></BODY></HTML> Tue, 06 Dec 2016 11:20:25 GMT https://community.nxp.com/t5/Layerscape/DDR3L-AC-DC-input-high-voltage-too-low/m-p/651227#M2256 markusthoss 2016-12-06T11:20:25Z https://community.nxp.com/t5/Layerscape/DDR3L-AC-DC-input-high-voltage-too-low/m-p/651228#M2257 <HTML><HEAD></HEAD><BODY><P>It is convenient to investigate the issue as Technical Case:</P><P><A href="https://community.freescale.com/thread/381898">https://community.freescale.com/thread/381898</A></P></BODY></HTML> Thu, 08 Dec 2016 06:25:51 GMT https://community.nxp.com/t5/Layerscape/DDR3L-AC-DC-input-high-voltage-too-low/m-p/651228#M2257 ufedor 2016-12-08T06:25:51Z