topic Which LS1046A clocks cannot be spread spectrum? in Layerscape

Which LS1046A clocks cannot be spread spectrum?

sabine_s — Tue, 24 Jan 2017 21:25:52 GMT

From the datasheet, it appears that it is okay for the Core and Platform clocks to be derived from a 100 MHz spread spectrum clock. The same appears to be true for the SerDes clock if used for PCIe.

Is it okay to use a SSC to derive a SerDes clock for SGMII?

Is it okay to use a SSC to derive the DDR clock?

Is it okay to use a SSC to derive the USB PHY clock?

Re: Which LS1046A clocks cannot be spread spectrum?

r8070z — Wed, 25 Jan 2017 12:56:26 GMT

Have a great day,

A spread-spectrum reference clock is permitted for the PCI Express and SYSCLK only. Notice that for the SerDes the data sheet says: “if spread-spectrum clocking is desired on a SerDes reference clock for the PCI Express protocol and the same reference clock is used for any other protocol, such as SATA or SGMII because of the SerDes lane usage mapping option, spread-spectrum clocking cannot be used at all.”

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Re: Which LS1046A clocks cannot be spread spectrum?

sabine_s — Wed, 25 Jan 2017 22:29:04 GMT

Thank you for your answer!

A spread-spectrum reference clock is permitted for the PCI Express and SYSCLK only.

According to Figure 4-3 on page 309 of the LS1046A Reference Manual, if a spread-spectrum clock is used for SYSCLK, it would mean that the USB PHY would be driven by a SSC clock. Is this okay?

Also, according to the same figure, the DDR PLL can have either SYSCLK or DDRCLK as its reference. Is it okay for the DDR PLL to have a SSC reference clock?