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    <title>topic Re: Using LS1043A with single chip 16bit DDR4 in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/Using-LS1043A-with-single-chip-16bit-DDR4/m-p/632910#M2036</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, a single 16-bit DDR4 chip can be used. DDR_SDRAM_CFG[DBW] defines DDR data bus width.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bulat&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 09 Mar 2017 06:30:21 GMT</pubDate>
    <dc:creator>Bulat</dc:creator>
    <dc:date>2017-03-09T06:30:21Z</dc:date>
    <item>
      <title>Using LS1043A with single chip 16bit DDR4</title>
      <link>https://community.nxp.com/t5/Layerscape/Using-LS1043A-with-single-chip-16bit-DDR4/m-p/632909#M2035</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Is it possible use&amp;nbsp;LS1043A with single chip 16bit DDR4 such us 512Mx16 Samsung&amp;nbsp;K4A8G165WB?&lt;/P&gt;&lt;P&gt;Shall I config memory controller for using another bit capacity?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Mar 2017 19:45:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Using-LS1043A-with-single-chip-16bit-DDR4/m-p/632909#M2035</guid>
      <dc:creator>andreyromanov</dc:creator>
      <dc:date>2017-03-08T19:45:44Z</dc:date>
    </item>
    <item>
      <title>Re: Using LS1043A with single chip 16bit DDR4</title>
      <link>https://community.nxp.com/t5/Layerscape/Using-LS1043A-with-single-chip-16bit-DDR4/m-p/632910#M2036</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, a single 16-bit DDR4 chip can be used. DDR_SDRAM_CFG[DBW] defines DDR data bus width.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bulat&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 09 Mar 2017 06:30:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Using-LS1043A-with-single-chip-16bit-DDR4/m-p/632910#M2036</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2017-03-09T06:30:21Z</dc:date>
    </item>
    <item>
      <title>Re: Using LS1043A with single chip 16bit DDR4</title>
      <link>https://community.nxp.com/t5/Layerscape/Using-LS1043A-with-single-chip-16bit-DDR4/m-p/632911#M2037</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Wasn't this possibility canceled? I'm confused. According to LS1043A Reference Manual Rev. 3 02/2017 the&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;DDR_SDRAM_CFG[DBW] has only one allowed (not reserved) value:&amp;nbsp;&lt;/SPAN&gt;&lt;EM&gt;01b - 32-bit bus is used&lt;/EM&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;. Moreover, in the same Reference Manual a DDR bus width is specified as 32/36 bit, 16-bit not mentioned.&amp;nbsp;The 16-bit width was maybe specified in some older Reference Manual, but I'm not sure, I cannot find the older document anymore.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Please, can you clarify this topic with respect to the current LS1043A Reference Manual (Rev. 3 02/2017)?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 24 May 2017 18:36:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Using-LS1043A-with-single-chip-16bit-DDR4/m-p/632911#M2037</guid>
      <dc:creator>cyrilstrejc</dc:creator>
      <dc:date>2017-05-24T18:36:12Z</dc:date>
    </item>
    <item>
      <title>Re: Using LS1043A with single chip 16bit DDR4</title>
      <link>https://community.nxp.com/t5/Layerscape/Using-LS1043A-with-single-chip-16bit-DDR4/m-p/632912#M2038</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The&amp;nbsp;destributor's support engenier told me:&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;SPAN lang="EN-US" style="font-size: 11pt;"&gt;Design team confirmed that rev 3 manual was corrected by mistake. I already mentioned required setup for 16-bit bus mode. For more information you can either use rev 1 or rev 2 LS1043A manuals, or LS1020A ref manual (all 16-bit instances in the DDR chapter are applicable to the LS1043A).&lt;/SPAN&gt;&lt;/EM&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 29 May 2017 18:38:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Using-LS1043A-with-single-chip-16bit-DDR4/m-p/632912#M2038</guid>
      <dc:creator>andreyromanov</dc:creator>
      <dc:date>2017-05-29T18:38:14Z</dc:date>
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