LS1021A PCIe iATU configuration

Tarek — Wed, 14 Sep 2016 12:52:07 GMT

The iATU configuration as shown by the devicetree programs only 2 outbound regions:

DeviceTree:

ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */

0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /*non-prefetchable memory */

I have confirmed this configuration by dumping the iATU registers.

Region1: Base 0x40 0001 0000 ==> Target 0x0000 0000

Region2: Base 0x40 4000 0000 ==> Target 0x4000 0000

So effectively the iATU is translating the 40-bit BAR space physical address to 32-bit PCIe address space which is fine.

My question is why the default configuration only programs the outbound and not the inbound as well?

Is it not expected that the PCIe device will write to this BAR space area at address 0x40 0000 0000?

What is a typical scenario for a PCIe NIC card for example in terms of the inbound/outbound messages?

Thanks

Re: LS1021A PCIe iATU configuration

r8070z — Thu, 15 Sep 2016 15:45:38 GMT

Have a great day,

Device tree is board specific. However the LS1021A has fixed memory map and there are 2 address ranges which can be used only for access to PCIe devices. 32 GB at 0x400000_0000 for the PCIe controller1 and 32 GB at 0x480000_0000 for the PCIe controller 2. So it is expected that for the LS1021A based board which use PCIe the device tree programs these 2 outbound regions. Notice both PCIe controllers can operate only as Root Complex. So NIC should be a PCIe End Point. NIC device driver can set inbound window if required. All MSI capable devices implement the MSI capability structure defined in the PCIe Specification. System software is ultimately responsible for enabling MSI support within a device.

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LS1021A PCIe iATU configuration

Re: LS1021A PCIe iATU configuration