LX2160A - Synchronous Ethernet (SyncE) RCLK

fdekeers — Mon, 24 Aug 2026 13:18:09 GMT

Hi,

I'm using an LX2160A board.

From my understanding, the SerDes modules can use Synchronous Ethernet (SyncE) and recover the clock from the input SerDes signal. This clock is then available as RCLK0/1, with the related SerDes being selected with the register RECOV_CLK_SEL_RCLK0/1.

Can this recovered clock signal then be used to drive the SerDes modules, either the one that it was recovered from or another ?
Potentially as reference clock for the PLLS / PLLF ?

Thanks in advance.

Re: LX2160A - Synchronous Ethernet (SyncE) RCLK

Bio_TICFSL — Tue, 25 Aug 2026 14:22:42 GMT

Hello,

No, RCLK0/1 cannot be fed directly back into the LX2160A SerDes as a reference clock for PLLS/PLLF. RCLK0 and RCLK1 are output-only pins on the LX2160A. The intended SyncE architecture requires routing RCLK0/1 through an external Jitter-Cleaner PLL first, and only then feeding the cleaned clock back as the SerDes reference clock (SD1_PLLS_REF_CLK_P/N, etc.).

Regards

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LX2160A - Synchronous Ethernet (SyncE) RCLK

Re: LX2160A - Synchronous Ethernet (SyncE) RCLK