https://community.nxp.com/t5/Layerscape/LS1043AXN8QQB-DVFS/m-p/2390217#M16766 <P><STRONG>500 MHz CPU runtime operation is supported if it is achieved by the CPU clock divider / cpufreq path, not by lowering the CGA PLL itself below 1 GHz.</STRONG></P> <P>For the PCIe abnormality: if the frequency change is done through the normal CPU DFS path, NXP evidence says&nbsp;<STRONG>only the CPU frequency is affected, while AHB/APB remains unchanged</STRONG>&nbsp;.&nbsp;Therefore PCIe should not be impacted by CPU DFS alone. If PCIe becomes abnormal, check whether the implementation is also changing platform/SYSCLK/PLL ratios, because the datasheet requires the platform clock settings to remain within their valid limits and states a PCIe platform-clock requirement for proper PCIe operation.</P> <P>LS1043A does support runtime CPU frequency scaling to 500 MHz, but the CGA PLL must stay at ≥1 GHz and PCIe/platform clocks must not be disturbed.</P> Fri, 03 Jul 2026 08:59:42 GMT yipingwang 2026-07-03T08:59:42Z https://community.nxp.com/t5/Layerscape/LS1043AXN8QQB-DVFS/m-p/2389683#M16764 <P>Dear support,</P><P>&nbsp;The customer used the LS1043AXN8QQB platform and set the CPU dynamic frequency adjustment from 1.6GHz to 800MHz and 500MHz. It was found that RCU stall and PCIE communication abnormality occurred when the CPU ran at 500MHz.</P><P>According to the RM and datasheet of the chip, LS1043 supports 1GHz to 1.6GHz. The official document does not mention the minimum supported frequency for dynamic frequency adjustment. It is uncertain whether 500MHz is supported?</P><P>Does LS1043A support dynamic frequency adjustment when the CPU is running normally?</P> Thu, 02 Jul 2026 10:34:33 GMT https://community.nxp.com/t5/Layerscape/LS1043AXN8QQB-DVFS/m-p/2389683#M16764 Nancy_LAN 2026-07-02T10:34:33Z https://community.nxp.com/t5/Layerscape/LS1043AXN8QQB-DVFS/m-p/2390217#M16766 <P><STRONG>500 MHz CPU runtime operation is supported if it is achieved by the CPU clock divider / cpufreq path, not by lowering the CGA PLL itself below 1 GHz.</STRONG></P> <P>For the PCIe abnormality: if the frequency change is done through the normal CPU DFS path, NXP evidence says&nbsp;<STRONG>only the CPU frequency is affected, while AHB/APB remains unchanged</STRONG>&nbsp;.&nbsp;Therefore PCIe should not be impacted by CPU DFS alone. If PCIe becomes abnormal, check whether the implementation is also changing platform/SYSCLK/PLL ratios, because the datasheet requires the platform clock settings to remain within their valid limits and states a PCIe platform-clock requirement for proper PCIe operation.</P> <P>LS1043A does support runtime CPU frequency scaling to 500 MHz, but the CGA PLL must stay at ≥1 GHz and PCIe/platform clocks must not be disturbed.</P> Fri, 03 Jul 2026 08:59:42 GMT https://community.nxp.com/t5/Layerscape/LS1043AXN8QQB-DVFS/m-p/2390217#M16766 yipingwang 2026-07-03T08:59:42Z