https://community.nxp.com/t5/Layerscape/LS1027A-boot-without-SD1-SD2-SerDes-reference-clocks-during/m-p/2380681#M16734 <DIV>Yes, the device can boot from SD with only DIFF_SYSCLK present — but only if your provisioning RCW disables the SerDes PLLs / SerDes protocols so the SoC does not expect those reference clocks during reset.</DIV> <DIV> <DIV> <UL> <LI>the SerDes lanes are configured as <STRONG>unused</STRONG>, and</LI> <LI>the SerDes PLLs are configured as <STRONG>powered down</STRONG> in RCW</LI> </UL> <DIV>What would prevent boot?</DIV> <DIV> <DIV>A. SerDes PLL left enabled in RCW while its refclk is absent</DIV> <DIV> <DIV>B. Provisioning RCW leaves any SerDes protocol active</DIV> <DIV> <DIV>C. Assuming DIFF_SYSCLK alone can substitute for any SerDes protocol automatically</DIV> </DIV> </DIV> </DIV> </DIV> </DIV> Fri, 12 Jun 2026 09:21:26 GMT yipingwang 2026-06-12T09:21:26Z https://community.nxp.com/t5/Layerscape/LS1027A-boot-without-SD1-SD2-SerDes-reference-clocks-during/m-p/2380074#M16730 <P>Hello,</P><P>I am working on a custom board based on the LS1027A.</P><P>During manufacturing, the board goes through an initial provisioning phase where the processor boots from an SD card. The only purpose of this boot is to program the eMMC with the final production software image.</P><P>In this provisioning stage, none of the SerDes interfaces are used. The board provides the mandatory SYSCLK, but the SD1_REF_CLK and SD2_REF_CLK signals are generated by an external PLL that requires software configuration before it can output the proper reference clocks.</P><P>My question is:</P><P><STRONG>Can the LS1027A successfully exit reset and boot from the SD card with only SYSCLK present, while SD1_REF_CLK and SD2_REF_CLK are absent?</STRONG></P><P>The idea would be:</P><OL><LI>Power up the board with SYSCLK available.</LI><LI>Boot the LS1027A from the SD card.</LI><LI>Configure the external PLL from software.</LI><LI>Enable the SerDes reference clocks.</LI><LI>Program the eMMC.</LI><LI>Switch to normal production boot from eMMC, where the PLL configuration and SerDes clocks are already available.</LI></OL><P>Are there any restrictions or boot-time requirements that would prevent the device from starting correctly when the SerDes reference clocks are not present at reset, assuming that no SerDes protocol is used during this initial provisioning phase?</P><P>Thank you for your help.</P><P>Best regards,</P> Thu, 11 Jun 2026 10:17:50 GMT https://community.nxp.com/t5/Layerscape/LS1027A-boot-without-SD1-SD2-SerDes-reference-clocks-during/m-p/2380074#M16730 AntoNico10 2026-06-11T10:17:50Z https://community.nxp.com/t5/Layerscape/LS1027A-boot-without-SD1-SD2-SerDes-reference-clocks-during/m-p/2380681#M16734 <DIV>Yes, the device can boot from SD with only DIFF_SYSCLK present — but only if your provisioning RCW disables the SerDes PLLs / SerDes protocols so the SoC does not expect those reference clocks during reset.</DIV> <DIV> <DIV> <UL> <LI>the SerDes lanes are configured as <STRONG>unused</STRONG>, and</LI> <LI>the SerDes PLLs are configured as <STRONG>powered down</STRONG> in RCW</LI> </UL> <DIV>What would prevent boot?</DIV> <DIV> <DIV>A. SerDes PLL left enabled in RCW while its refclk is absent</DIV> <DIV> <DIV>B. Provisioning RCW leaves any SerDes protocol active</DIV> <DIV> <DIV>C. Assuming DIFF_SYSCLK alone can substitute for any SerDes protocol automatically</DIV> </DIV> </DIV> </DIV> </DIV> </DIV> Fri, 12 Jun 2026 09:21:26 GMT https://community.nxp.com/t5/Layerscape/LS1027A-boot-without-SD1-SD2-SerDes-reference-clocks-during/m-p/2380681#M16734 yipingwang 2026-06-12T09:21:26Z