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    <title>topic Re: LS1043 PORRESET_B vs. HRESET_B difference to DDR controller in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1043-PORRESET-B-vs-HRESET-B-difference-to-DDR-controller/m-p/2374718#M16718</link>
    <description>&lt;P&gt;thank you very much. It helped me a lot.&lt;/P&gt;</description>
    <pubDate>Tue, 02 Jun 2026 02:42:44 GMT</pubDate>
    <dc:creator>lingjun</dc:creator>
    <dc:date>2026-06-02T02:42:44Z</dc:date>
    <item>
      <title>LS1043 PORRESET_B vs. HRESET_B difference to DDR controller</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043-PORRESET-B-vs-HRESET-B-difference-to-DDR-controller/m-p/2374337#M16716</link>
      <description>&lt;P&gt;Hi NXP expert :&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;I have a board that uses the LS1043 processor, and this board's CPU may have power integrity issues. I've found that when the DDR controller causes a CPU exception due to power integrity problems, the watchdog HRESET_B reset sometimes fails to successfully reset the CPU. Only a&amp;nbsp; PORRESET_B power reset can successfully reset it.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; I would like to know: for the DDR controller of the LS1043, what is the difference between these PORRESET_B and HRESET_B resets?&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;thanks a lot ~&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 01 Jun 2026 08:47:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043-PORRESET-B-vs-HRESET-B-difference-to-DDR-controller/m-p/2374337#M16716</guid>
      <dc:creator>lingjun</dc:creator>
      <dc:date>2026-06-01T08:47:19Z</dc:date>
    </item>
    <item>
      <title>Re: LS1043 PORRESET_B vs. HRESET_B difference to DDR controller</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043-PORRESET-B-vs-HRESET-B-difference-to-DDR-controller/m-p/2374690#M16717</link>
      <description>&lt;UL&gt;
&lt;LI&gt;
&lt;P&gt;&lt;STRONG&gt;PORRESET_B&lt;/STRONG&gt; = &lt;EM&gt;full chip cold reset&lt;/EM&gt;&lt;BR /&gt;→ Resets &lt;STRONG&gt;everything&lt;/STRONG&gt;, including DDR controller logic, PHY, internal state machines, PLLs, and I/O calibration.&lt;/P&gt;
&lt;/LI&gt;
&lt;LI&gt;
&lt;P&gt;&lt;STRONG&gt;HRESET_B&lt;/STRONG&gt; = &lt;EM&gt;core/system warm reset&lt;/EM&gt;&lt;BR /&gt;→ Resets &lt;STRONG&gt;CPU cores and most digital logic&lt;/STRONG&gt;, but &lt;STRONG&gt;does NOT fully reset DDR PHY and some analog / training state&lt;/STRONG&gt;.&lt;/P&gt;
&lt;/LI&gt;
&lt;/UL&gt;
&lt;P&gt;&lt;SPAN&gt;Therefore: If DDR or its PHY enters an invalid state (e.g., due to power integrity causing training corruption), &lt;/SPAN&gt;&lt;STRONG style="font-family: inherit;"&gt;HRESET_B cannot recover it&lt;/STRONG&gt;&lt;SPAN&gt;, but &lt;/SPAN&gt;&lt;STRONG style="font-family: inherit;"&gt;PORRESET_B can&lt;/STRONG&gt;&lt;SPAN&gt;.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 02 Jun 2026 02:05:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043-PORRESET-B-vs-HRESET-B-difference-to-DDR-controller/m-p/2374690#M16717</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2026-06-02T02:05:00Z</dc:date>
    </item>
    <item>
      <title>Re: LS1043 PORRESET_B vs. HRESET_B difference to DDR controller</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043-PORRESET-B-vs-HRESET-B-difference-to-DDR-controller/m-p/2374718#M16718</link>
      <description>&lt;P&gt;thank you very much. It helped me a lot.&lt;/P&gt;</description>
      <pubDate>Tue, 02 Jun 2026 02:42:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043-PORRESET-B-vs-HRESET-B-difference-to-DDR-controller/m-p/2374718#M16718</guid>
      <dc:creator>lingjun</dc:creator>
      <dc:date>2026-06-02T02:42:44Z</dc:date>
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