DDR bring-up on NXP based SoM (Layerscape SoC)

chandrest — Wed, 20 May 2026 10:02:05 GMT

In a few months at my company we will have our new SoMs (built on the top of NXP LS1028 SoC) ready to bring-up. That's way I would to get some knowledge from you - more experienced developer - how do you approach DDR bring-up? What tools do use use? How do you perform DDR initialization? What steps do you perform? What are the common pitfalls regarding DDR bring up? What should I be aware of?

Re: DDR bring-up on NXP based SoM (Layerscape SoC)

June_Lu — Thu, 21 May 2026 07:16:45 GMT

For the DDR validation, please kindly follow the QCVS_DDR_User_Guide.

After successfully finishing the QCVS validation, clicke the icon of "Generate processor expert code" to generate the optimal timing pararamers in <CodeWarrior-workplace>\<Project-name>\Generated_Code\ddr_init1.c,then integrate the optimized timing parameters into ATF ddr_init.c.

The QCVS DDR is one tool of codewarrior Developer Suite Level.

You can also download codewarrior Developer Suite Level Evaluation Edition from the link below.

https://www.nxp.com/design/software/development-software/codewarrior-development-tools/codewarrior-network-applications/codewarrior-development-suites-for-networked-applications:CW-DS-NETAPPS

The Evaluation Edition is free to use but has a time limitation.

The debug tool is used to connect the LS1028A customer board and the codewarrior Developer Suite Level, please kindly find the tool in below link:

https://www.nxp.com/design/design-center/development-boards-and-designs/CW_TAP

CodeWarrior TAP High Performance Probe Base unit, supports Ethernet and USB (order tip separately).

CWH-CTP-BASE-HE

CWH-CTP-CTX10-YE

Layerscape processor (Coretex 10 pin)

The DDR layout should follow the AN5097

AN5097, Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces

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DDR bring-up on NXP based SoM (Layerscape SoC)

Re: DDR bring-up on NXP based SoM (Layerscape SoC)