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    <title>LayerscapeのトピックRe: LS1043A is SEC a requirement for Secure Boot?</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1043A-is-SEC-a-requirement-for-Secure-Boot/m-p/2356633#M16660</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;If the LS1043A silicon lacks the SEC engine, it is physically incapable of triggering the ROM-based logic required to start a secure chain. The Arm CoT/mbedtls path in LSDK is not a "workaround" for missing hardware; it is simply a different software architecture for chips that &lt;EM class="eujQNb" data-processed="true" data-complete="true" data-sfc-cb="" data-sfc-root="c"&gt;do&lt;/EM&gt; have the necessary security hardware.&lt;/P&gt;
&lt;P&gt;regards&lt;/P&gt;</description>
    <pubDate>Mon, 27 Apr 2026 14:43:34 GMT</pubDate>
    <dc:creator>Bio_TICFSL</dc:creator>
    <dc:date>2026-04-27T14:43:34Z</dc:date>
    <item>
      <title>LS1043A is SEC a requirement for Secure Boot?</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-is-SEC-a-requirement-for-Secure-Boot/m-p/2355457#M16643</link>
      <description>&lt;P&gt;Since the LS1043A can come with either SEC enabled, or SEC disabled.&lt;/P&gt;&lt;P&gt;Is it a hard requirement that SEC be enabled for Secure Boot?&lt;/P&gt;&lt;P&gt;If we have an LS1043A that already has SEC disabled from NXP can Secure Boot still be achieved? Documentation is unclear, but seems like Secure Boot is still available even if SEC is not. Is this correct?&lt;/P&gt;</description>
      <pubDate>Thu, 23 Apr 2026 22:18:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-is-SEC-a-requirement-for-Secure-Boot/m-p/2355457#M16643</guid>
      <dc:creator>endrunner_smw</dc:creator>
      <dc:date>2026-04-23T22:18:50Z</dc:date>
    </item>
    <item>
      <title>Re: LS1043A is SEC a requirement for Secure Boot?</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-is-SEC-a-requirement-for-Secure-Boot/m-p/2355919#M16647</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;&lt;MARK class="HxTRcb" data-sae="" data-complete="true" data-sfc-cb="" data-sfc-root="c"&gt;&lt;SPAN data-subtree="aimfl"&gt;No, it is &lt;/SPAN&gt;&lt;STRONG class="Yjhzub" data-complete="true" data-sfc-cb="" data-sfc-root="c"&gt;not correct&lt;/STRONG&gt; that Secure Boot is available if the SEC engine is disabled&lt;/MARK&gt;. For the LS1043A, having the SEC engine (security acceleration) enabled is a &lt;STRONG class="Yjhzub" data-processed="true" data-complete="true" data-sfc-cb="" data-sfc-root="c"&gt;hard requirement&lt;/STRONG&gt; for establishing a hardware-rooted Secure Boot.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards&lt;/P&gt;</description>
      <pubDate>Fri, 24 Apr 2026 14:08:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-is-SEC-a-requirement-for-Secure-Boot/m-p/2355919#M16647</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2026-04-24T14:08:22Z</dc:date>
    </item>
    <item>
      <title>Re: LS1043A is SEC a requirement for Secure Boot?</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-is-SEC-a-requirement-for-Secure-Boot/m-p/2356047#M16649</link>
      <description>&lt;P&gt;Ok, so a LS1043ASN7MNLB is not capable of secure boot with arm trusted firmware, correct?&lt;/P&gt;&lt;P&gt;A LS1043ASEN7MNLB would be capable of secure boot with arm trusted firmware, because it has the SEC enabled, correct?&lt;/P&gt;&lt;P&gt;Now you said that for the non-SEC chip it is not capable of a 'hardware-rooted' secure boot. Does that mean a software version / 'software-rooted' of secure boot could work? In the LSDK 21.08 it does also mention instead of NXP CoT there is Arm CoT that utilizes mbedtls. However, it looks like in the documentation that it does not support the LS1043A chip.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Just trying to get some clarification.&lt;/P&gt;&lt;P&gt;Thank you for the reply.&lt;/P&gt;</description>
      <pubDate>Sat, 25 Apr 2026 00:06:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-is-SEC-a-requirement-for-Secure-Boot/m-p/2356047#M16649</guid>
      <dc:creator>endrunner_smw</dc:creator>
      <dc:date>2026-04-25T00:06:12Z</dc:date>
    </item>
    <item>
      <title>Re: LS1043A is SEC a requirement for Secure Boot?</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-is-SEC-a-requirement-for-Secure-Boot/m-p/2356633#M16660</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;If the LS1043A silicon lacks the SEC engine, it is physically incapable of triggering the ROM-based logic required to start a secure chain. The Arm CoT/mbedtls path in LSDK is not a "workaround" for missing hardware; it is simply a different software architecture for chips that &lt;EM class="eujQNb" data-processed="true" data-complete="true" data-sfc-cb="" data-sfc-root="c"&gt;do&lt;/EM&gt; have the necessary security hardware.&lt;/P&gt;
&lt;P&gt;regards&lt;/P&gt;</description>
      <pubDate>Mon, 27 Apr 2026 14:43:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-is-SEC-a-requirement-for-Secure-Boot/m-p/2356633#M16660</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2026-04-27T14:43:34Z</dc:date>
    </item>
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