LayerscapeのトピックRe: Cannot set CONFIG_DDR_NODIMM

Cannot set CONFIG_DDR_NODIMM

bezeria — Wed, 25 Feb 2026 17:05:56 GMT

I am using latest flexbuild from https://github.com/NXP/flexbuild

I am modifying `flexbuild/components_lsdk2512/bsp/atf/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk`

to include `CONFIG_DDR_NODIMM := 1`

Afterwards, I am rebuilding atf with `bld atf -m lx2160ardb -b sd` , but I am getting the following error:

Building ATF for lx2160ardb sd boot
cp: cannot stat 'build/lx2160ardb/release/bl2_sd*.pbl': No such file or directory
make[1]: *** [/home/bezeria/repos/flexbuild/src/bsp/atf.mk:107: atf] Error 1
make: *** [Makefile:14: atf] Error 2

Re: Cannot set CONFIG_DDR_NODIMM

LFGP — Thu, 26 Feb 2026 17:06:42 GMT

Dear @bezeria ,

The LX2160 platform doesn't have support for NODIMM out of the box.

you need to add your DDR_NODIMM_Custom file to ATF.

Please use the DDRv tool to obtain the ddr_init.c acoording to your needs, then add it to the ATF.

LFGP

Re: Cannot set CONFIG_DDR_NODIMM

bezeria — Thu, 26 Feb 2026 17:40:06 GMT

I have the values for CONFIG_DDR_NODIMM for the ATF.

I place them to ddr_init.c then place CONFIG_DDR_NODIMM:=1 to platform.mk, and issue

bld bsp -m lx2160ardb

But I get the error described in the previous post.

Re: Cannot set CONFIG_DDR_NODIMM

bezeria — Sat, 28 Feb 2026 18:48:56 GMT

One problem is fixed when I updated the ddr_get_ddr_params in ddr_init.c

The atf compiles now succesfully, but when I deploy it, I get

NOTICE: BL2: Built : 18:50:19, Feb 28 2026
NOTICE: Fixed DDR Config 1
ERROR: DDR Clk: MCLK cycle is 625 ps.
ERROR: DDR Clk is faster than DIMM can support.
ERROR: Execution FW failed (error code -5)
ERROR: Calculating DDR PHY registers failed.

The DIMM I am deploying is 2933Mhz (lower than the default 3200Mhz); I have already edited the RCW to lower the DDR controller to 2900 and even 2600. The error still happens.

How can I correctly configure the DDR clock?

Re: Cannot set CONFIG_DDR_NODIMM

bezeria — Sat, 28 Feb 2026 22:31:16 GMT

I managed to fix the MCLK cycle problem, but I arrived to a new problem of interleaving mode. I am using the default 2 ddr controllers NUM_OF_DDRC . The error is:

NOTICE: BL2: Built : 23:02:58, Feb 28 2026
NOTICE: Fixed DDR Config 1
ERROR: Unknown interleaving modeERROR: Assigning address error

This happens with 2 or 4 DIMM configuration (info.dimm_on_ctlr = DDRC_NUM_DIMM = 2 or 4)