Layerscape中的主题 Re: Setting GPIO pin as OUTPUT during power-on-reset

Setting GPIO pin as OUTPUT during power-on-reset

dz_tiger — Fri, 13 Feb 2026 21:57:04 GMT

Hi,

I added the following code into RCW,

.pbi

// Write to CCSR (Configuration and Control Space)
// Syntax: <address> <value>

write 0x02310000, 0x1D0000 // Set GPIO GPIO2_15,13,12,11

// Wait command to allow hardware to settle
wait 1000

// Final command to flush PBI
flush

.end

Can someone review my changes?

After I flashed firmware, it fails to reset the board. On board RED led keeps flashing. I had to re-program the board. But BANK-0 fails, only BANK-1 still programmable.

Not sure, if the above code is causing the problem and damaging bank-0?

Thank you,

dz_tiger

Re: Setting GPIO pin as OUTPUT during power-on-reset

Bio_TICFSL — Mon, 16 Feb 2026 14:13:04 GMT

Hello,

The code you added to the RCW

PBI might be the direct cause of your board's failure to reset and the subsequent issues with Bank 0 programming. Modifying crucial early boot configurations like GPIO settings via PBI commands carries significant risk.

Potential Issues with the PBI Code

Incorrect Register Access: The address 0x02310000 likely points to a critical configuration and control status register (CCSR). Writing an incorrect value to reserved bits or a sensitive control register (e.g., related to the boot device, clocking, or reset logic) during the early boot phase can cause the processor to enter an unrecoverable state or a boot loop immediately after the PBI command is processed.
GPIO Misconfiguration: The comment // Set GPIO GPIO2_15,13,12,11 suggests you are trying to configure specific GPIO pins. If these pins are multiplexed with essential boot-strap functions (like those used for the flash memory interface or JTAG/debug interface) and are incorrectly set as outputs with a specific value, the board's ability to communicate with the boot flash (Bank 0) or the programming tools can be compromised.
Timing Issues: The wait 1000 command adds a delay, but if the preceding write command has already caused a critical error or a boot-loop, the processor may never reach the wait or flush commands.

Why Bank 0 Might Be Affected

The PBL (Pre-Boot Loader), which processes the RCW and PBI commands, runs early in the boot sequence and typically loads from the primary boot device, likely Bank 0 of your flash memory. A faulty PBI command stored in Bank 0 can prevent the successful execution of the boot process from that bank, leading to the symptoms you described (red LED flashing, failure to reset).

Bank 1 might still be programmable because it likely contains either the original, working firmware or is not part of the primary boot sequence that is failing.

Recommended Actions and Review

Remove the Suspect PBI Command: The immediate next step is to revert the changes. Re-program Bank 1 with your original, working firmware and ensure the board boots correctly from Bank 1.
Debug Incrementally: To identify the exact command causing the issue, add PBI commands one by one to a clean RCW file and test the board's boot process after each addition. This will help pinpoint which specific command is the culprit.
Consult Documentation: Refer to the official NXP Community or the specific SoC's Reference Manual to verify the correct addresses and values for configuring the GPIO registers and ensuring you are not using reserved bits.
Use Official Tools: Utilize the QCVS PBL tool if possible, as it helps prevent violating documented PBL configuration constraints and errata.
Seek Expert Help: Post your detailed issue and board type on the NXP Community forum to get assistance from application engineers who can provide specific guidance for your hardware.

Conclusion: Your PBI changes are highly likely the cause of the problem. Revert the changes immediately and use the iterative debugging approach to safely incorporate the desired GPIO settings

Regards

Re: Setting GPIO pin as OUTPUT during power-on-reset

dz_tiger — Tue, 17 Feb 2026 14:20:41 GMT

Hi Bio_Ticfsl,

Appreciate your detailed explanations.

I had programed BANK-1 with a working image, and it is booted from BANK-1.

First I want to reprogram bank-0. When I booted from BANK-1, ( using Jumper to select BANK-1), but I can only do

sf probe 0:0, ( I assume this is the currently running bank, i.e. original bank-1)

sf probe 0:1 fails. So I am not sure if the original bank-0 is 'damaged'? or I don't know a way to reprogram the original bank-0.

Thank you for your support!

dz_tiger

Re: Setting GPIO pin as OUTPUT during power-on-reset

Bio_TICFSL — Wed, 18 Feb 2026 14:15:11 GMT

Hi,

To reprogram Bank-0 while booted from Bank-1 on an NXP S32G device, you typically need to access the inactive chip select or ensure the U-Boot device tree recognizes multiple flash devices. The failure of sf probe 0:1 often occurs because the SPI controller is configured to only recognize the primary flash chip or because of a hardware/software configuration mismatch.

Regards

Re: Setting GPIO pin as OUTPUT during power-on-reset

dz_tiger — Wed, 18 Feb 2026 17:56:29 GMT

I have resolved sf probe 0:1 issue.
I programmed xspi_boot.img into BANK-1, but qixis_reset altbank unknown u-boot command. I guess it is not included in the uboot built.
Is there any way to set reset control registers to boot from bank-1 ( cannot find the register from ref man). If bank-1 fails to boot, will it automatically fall back to BANK-0.

Re: Setting GPIO pin as OUTPUT during power-on-reset

dz_tiger — Wed, 18 Feb 2026 21:16:47 GMT

Also, after I added PBI code, BANK-0 fails to reset ( red led keeps flashing). But I cannot restore it to factory default rcw with CodeWarrior Programmer. I am wondering what's the difference between a bad rcw bank vs. a new empty bank from Code Warrior Programmer point of view?
Thank you,