<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LayerscapeのトピックRe: ls1046 ddr4 frequency at calibration process</title>
    <link>https://community.nxp.com/t5/Layerscape/ls1046-ddr4-frequency-at-calibration-process/m-p/2317603#M16466</link>
    <description>&lt;P&gt;I understand,thank you very much!&lt;/P&gt;</description>
    <pubDate>Fri, 13 Feb 2026 07:06:59 GMT</pubDate>
    <dc:creator>altu</dc:creator>
    <dc:date>2026-02-13T07:06:59Z</dc:date>
    <item>
      <title>ls1046 ddr4 frequency at calibration process</title>
      <link>https://community.nxp.com/t5/Layerscape/ls1046-ddr4-frequency-at-calibration-process/m-p/2316893#M16462</link>
      <description>&lt;P&gt;Good day!&lt;/P&gt;&lt;P&gt;I'm calibrating DDR4 memory on my custom ls1046-based board.&lt;/P&gt;&lt;P&gt;My RCW settings:&lt;/P&gt;&lt;P&gt;SYS_PLL_RAT=6&lt;BR /&gt;MEM_PLL_RAT=12&lt;BR /&gt;CGA_PLL1_RAT=12&lt;BR /&gt;CGA_PLL2_RAT=10&lt;/P&gt;&lt;P&gt;SYSCLK_FREQ=600&lt;/P&gt;&lt;P&gt;DDR_REFCLK_SEL=1&lt;BR /&gt;DDR_FDBK_MULT=2&lt;/P&gt;&lt;P&gt;My SYSCLK = 100 Mhz&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ddr1.png" style="width: 918px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/376629iB79702F163363F8C/image-size/large?v=v2&amp;amp;px=999" role="button" title="ddr1.png" alt="ddr1.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;ddr1.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;I expect to have:&lt;/P&gt;&lt;P&gt;DDR bus clock = &lt;STRONG&gt;600&lt;/STRONG&gt; Mhz and DDR rate = &lt;STRONG&gt;1200&lt;/STRONG&gt; MT/s , but I have&amp;nbsp;DDR bus clock = &lt;STRONG&gt;625&lt;/STRONG&gt; Mhz and DDR rate = &lt;STRONG&gt;1250&lt;/STRONG&gt; MT/s.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ddr2.png" style="width: 868px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/376630i7710B7EF546185FE/image-size/large?v=v2&amp;amp;px=999" role="button" title="ddr2.png" alt="ddr2.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;ddr2.png&lt;/span&gt;&lt;/span&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;So the question is - why do we have addtional 25 Mhz / 50 MT/s ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 12 Feb 2026 07:38:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/ls1046-ddr4-frequency-at-calibration-process/m-p/2316893#M16462</guid>
      <dc:creator>altu</dc:creator>
      <dc:date>2026-02-12T07:38:24Z</dc:date>
    </item>
    <item>
      <title>Re: ls1046 ddr4 frequency at calibration process</title>
      <link>https://community.nxp.com/t5/Layerscape/ls1046-ddr4-frequency-at-calibration-process/m-p/2317554#M16465</link>
      <description>&lt;P style="margin: 0in; font-family: Calibri; font-size: 11.0pt;"&gt;LS1046A DDR4 Min Freq.(MHz) is 650MHz, as specified in the &lt;A href="https://www.nxp.com/docs/en/data-sheet/LS1046A.pdf" target="_blank"&gt;LS1046A, LS1026A Data Sheet&lt;/A&gt;, Table 141. Memory bus clocking specifications&lt;/P&gt;
&lt;P style="margin: 0in; font-family: Calibri; font-size: 11.0pt;"&gt;Kindly refer to this requirement in your design.&lt;/P&gt;
&lt;P style="margin: 0in; font-family: Calibri; font-size: 11.0pt;"&gt;Thanks&lt;/P&gt;</description>
      <pubDate>Fri, 13 Feb 2026 05:27:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/ls1046-ddr4-frequency-at-calibration-process/m-p/2317554#M16465</guid>
      <dc:creator>June_Lu</dc:creator>
      <dc:date>2026-02-13T05:27:57Z</dc:date>
    </item>
    <item>
      <title>Re: ls1046 ddr4 frequency at calibration process</title>
      <link>https://community.nxp.com/t5/Layerscape/ls1046-ddr4-frequency-at-calibration-process/m-p/2317603#M16466</link>
      <description>&lt;P&gt;I understand,thank you very much!&lt;/P&gt;</description>
      <pubDate>Fri, 13 Feb 2026 07:06:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/ls1046-ddr4-frequency-at-calibration-process/m-p/2317603#M16466</guid>
      <dc:creator>altu</dc:creator>
      <dc:date>2026-02-13T07:06:59Z</dc:date>
    </item>
  </channel>
</rss>

