LayerscapeのトピックRe: DDR4 calibration issues on LS1046 custom board

DDR4 calibration issues on LS1046 custom board

altu — Sat, 07 Feb 2026 08:44:13 GMT

Good day!

We are trying to bring up our custom LS1046-based board up and stucked with DDR4 calibration procedure.

SPD data of the modules is red successfully, calibration process starts successfully too, but after that it fails with this reason(log from CodeWarrior

############################### Run 1

Result for: wrlvl_searcher

######################################

Test result: [

============================================================

Updated:

WRLVL_CNTL = 0x8655F605, WRLVL_CNTL_2 = 0x00000000,
WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated:

WRLVL_CNTL = 0x8655F60A, WRLVL_CNTL_2 = 0x0B0B0C0F,
WRLVL_CNTL_3 = 0x0F10110D, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated:

WRLVL_CNTL = 0x8655F60A, WRLVL_CNTL_2 = 0x0B0B0C0F,
WRLVL_CNTL_3 = 0x0F101115, SDRAM_CLK_CNTL = 0x02800000

============================================================

Updated:

WRLVL_CNTL = 0x8655F60A, WRLVL_CNTL_2 = 0x0B0B0C0F,
WRLVL_CNTL_3 = 0x0F10111D, SDRAM_CLK_CNTL = 0x02800000

Write Leveling start values are correct and require no further modification,
but the test failed due to other issues.

Most common failure causes:

-incorrect values configured in DDR4 DQn_MAP registers
-incorrect ODT values
-incorrect driver strength selected
-incorrect timing values selected for Timing Configuration 0 properties (TIMING_CFG_0 register)

<<Test failed!>>

{{Write Leveling start values are correct and require no further modification,
but the test failed due to other issues.}}

Err. capture registers:

0xE20, 0xDEADBEEF
0xE24, 0xDEADBEEF
0xE28, 0x00000000
0xE40, 0x00000000
0xE44, 0x00000000
0xE48, 0x0000001D
0xE4C, 0x60FF2001
0xE50, 0x00001FC0
0xE54, 0x00000000
0xE58, 0x00010000

############################################

DQ mapping seems to be OK - we have 1:1 mapping from CPU to DDR slot, so we use DQ mappings from DDR module SPD without changing.

What can be the problem?

Re: DDR4 calibration issues on LS1046 custom board

June_Lu — Mon, 09 Feb 2026 11:06:14 GMT

Is there available RCW on the customer board?

Has the ASLEEP led turned on and off?

What's the frequency of the DDR clock?

Thanks

Re: DDR4 calibration issues on LS1046 custom board

June_Lu — Tue, 10 Feb 2026 07:36:19 GMT

1.The QCVS does not support hardcoded RCW official, valid RCW has to be presented in the RCW source flash or SD card.

Would you kindly program the RCW into the flash first, and then do the QCVS DDR validation.

2.Run the command below in the CCS:

(bin) 42 % delete all

(bin) 43 % config cc cwtap

(bin) 44 % show cc

(bin) 45 % ccs::config_chain {ls1043a dap sap2}

(bin) 46 % display ::ccs::get_config_chain

(bin) 47 % ccs::reset_to_debug

Send the logs to me.

3.would you kindly share the schematics and confirm the layout follow the

AN5097, Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces

Thanks

Re: DDR4 calibration issues on LS1046 custom board

altu — Thu, 12 Feb 2026 20:57:15 GMT

The problem was solved by updating to new version of QCVS(4.27.0)