Layerscape中的主题 Re: LX2160A DDR memory connections

LX2160A DDR memory connections

kurokawa — Tue, 03 Feb 2026 08:18:14 GMT

Regarding DDR memory connections to the LX2160A

I'm considering connecting nine 8-bit DDR4 memory modules (8 x 9 = 72 bits) to the LX2160, and dividing them into TOP and BOTTOM locations to minimize the implementation area.

In this case, would it be possible to use address mirroring to configure TOP = CS0 as five chips and BOTTOM = CS1 as four chips?

Re: LX2160A DDR memory connections

shengzhou_liu — Wed, 04 Feb 2026 09:55:52 GMT

Hi @kurokawa

LX2160A supports DDR address mirroring.

Asymmetric population (5 devices on CS0 and 4 devices on CS1) is not feasible.
Address mirroring should be applied in a balanced topology.
for the specific chip-selection, it should be 64-bit data width, not 8x 5-chip = 40-bits or 8x 4-chips = 32-bits

there are 3 topologies:

way 1: (single-controller and single-rank, without address mirroring)
TOP: 5 x8 DRAM parts for data + 1 x8 DRAM part for ECC with CS0
BOTTOM: 4 x8 DRAM parts for data with CS0

way 2: (single-controller and dual-ranks, with address mirroring)
TOP: 4 x16 DRAM parts for data + 1 x16 DRAM part(only 8-bits used) for ECC with CS0 of DDRC1
BOTTOM: 4 x16 DRAM parts for data + 1 x16 DRAM part(only 8-bits used) for ECC with CS1 of DDRC1

way 3 (dual-controllers and single-rank for better performance):
TOP: 4 x16 DRAM parts for data + 1 x16 DRAM part(only 8-bits used) for ECC with CS0 of DDRC1
BOTTOM: 4 x16 DRAM parts for data + 1 x16 DRAM part(only 8-bits used) for ECC with CS0 of DDRC2

if .mirrored_dimm = 1 in mocked SPD way in ATF, DDR driver sets DDR_SDRAM_CFG_2[MD_EN] = 1.

Re: LX2160A DDR memory connections

kurokawa — Tue, 03 Feb 2026 11:11:45 GMT

Thank you for your reply.

Just to be sure, let me confirm way 2.

If using 8-bit chips and using one controller, is it possible to perform address mirroring by placing 9 chips on the TOP and 9 chips on the BOTTOM (18 chips in total)?

Re: LX2160A DDR memory connections

shengzhou_liu — Wed, 04 Feb 2026 09:57:15 GMT

Yes, it is feasible to that using 8-bit chips and one controller to perform address mirroring by placing 9 chips on the TOP and 9 chips on the BOTTOM.

But from the perspective of performance, the bandwidth performance of using dual-controllers with single-rank is better than that of using single-controller with dual-ranks.