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    <title>LayerscapeのトピックRe: codewarrior fails to write memory on LS1043A without encryption</title>
    <link>https://community.nxp.com/t5/Layerscape/codewarrior-fails-to-write-memory-on-LS1043A-without-encryption/m-p/2297550#M16417</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEQAA" data-processed="true"&gt;
&lt;DIV style="display: contents;" data-subtree="aimfl,mfl" data-processed="true"&gt;The failure to recover bricked LS1043A boards without encryption support (non-secure SoC) often stems from the inability of the JTAG debugger to initialize the QSPI flash/IFC controller when the RCW is entirely missing, even when&lt;/DIV&gt;
&lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;USE_SAFE_RCW&lt;/CODE&gt; is set to &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;True&lt;/CODE&gt;. Because non-secure SoCs may behave differently than secure ones regarding RCW loading, you may need to explicitly configure the initialization script to handle the blank state.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_d" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_c/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAIQAA" data-processed="true"&gt;Here is a guide to testing modifications in your initialization script and verifying the RCW override.&lt;/DIV&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;1. Test Modifications in the Initialization Script&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAQQAA" data-processed="true"&gt;When the NOR is erased, the board cannot boot. The CodeWarrior &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;USE_SAFE_RCW&lt;/CODE&gt; aims to supply a temporary RCW via JTAG, but it might not be configuring the memory interface correctly for your board.&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-processed="true"&gt;
&lt;LI data-hveid="CAUQAA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Set &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;BOOT_CHIP_SELECT&lt;/CODE&gt; to 2:&lt;/STRONG&gt; In the initialization script (&lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;.py&lt;/CODE&gt;), set &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;BOOT_CHIP_SELECT = 2&lt;/CODE&gt;. This tells the CodeWarrior script to use the hard-coded RCW (via RCW override) rather than expecting the board to read one from a flash bank.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAUQAQ" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Set &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;QSPI_BOOT = 1&lt;/CODE&gt; or &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;0&lt;/CODE&gt;:&lt;/STRONG&gt; If you are using QSPI (common in modern custom boards), ensure &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;QSPI_BOOT&lt;/CODE&gt; is set correctly. Note that some forum posts suggest that if QSPI is too fast, the connection fails. You may need to enable a "Half Speed" option in the QSPI initialization section of the script.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAUQAg" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Set &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;BOARD_REV_PD = True&lt;/CODE&gt;:&lt;/STRONG&gt; This setting is sometimes required to ensure the correct memory controller parameters are used during the recovery process.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAUQAw" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;DDR Initialization:&lt;/STRONG&gt; Ensure you have &lt;STRONG class="Yjhzub" data-processed="true"&gt;deleted&lt;/STRONG&gt; any DDR initialization code in your custom initialization script. The flash programmer must run using on-chip RAM (OCRAM) because the DDR is not initialized when the board is in a "broken" state.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAUQBA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Validate JTAG Chain:&lt;/STRONG&gt; Ensure the LS1043A is the &lt;STRONG class="Yjhzub" data-processed="true"&gt;first device&lt;/STRONG&gt; in the JTAG chain. If an FPGA or CPLD is first, the RCW override (which communicates directly with the SoC) might fail.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_1f" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_1e/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;2. How to Verify RCW Override is Working&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAcQAA" data-processed="true"&gt;To confirm that the &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;USE_SAFE_RCW = True&lt;/CODE&gt; is actually working, you can try the following:&lt;/DIV&gt;
&lt;OL class="IaGLZe VimKh" data-processed="true"&gt;
&lt;LI data-hveid="CAgQAA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Check the "Core not responding" error:&lt;/STRONG&gt; If you still see "Failed to write memory at address..." or "Core not responding" after enabling &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;USE_SAFE_RCW&lt;/CODE&gt;, it means the RCW override failed.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAgQAQ" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Verify using "Write Reset Configuration Word" task:&lt;/STRONG&gt; In CodeWarrior, try executing the specific "Write Reset Configuration Word" debug task rather than the full Flash Programmer. If this task passes, it indicates the JTAG probe is successfully writing the override.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAgQAg" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Check &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;ccs::config_chain&lt;/CODE&gt;:&lt;/STRONG&gt; Use &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;ccs::config_chain{ ls1043a dap sap2}&lt;/CODE&gt; in the script to confirm the debugger is communicating with the SoC properly.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_26" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_25/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/OL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;3. Alternative Recovery Approach&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAoQAA" data-processed="true"&gt;If &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;USE_SAFE_RCW&lt;/CODE&gt; still fails, you can try to force the board into a hard-coded RCW mode via physical switches, which might provide a more stable JTAG connection for flashing:&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-processed="true"&gt;
&lt;LI data-hveid="CAsQAA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Configure the DIP switches on your board to boot from a "Hard-coded RCW" source (typically &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;cfg_rcw_src&lt;/CODE&gt; to 0 or another hard-coded value, check your schematic for &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;cfg_rcw_src&lt;/CODE&gt; pins). This allows the board to boot without a valid flash image.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAsQAQ" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Once in this mode, try connecting and flashing using the "RAM Boot" method (loading a small PBL into RAM and then flashing).&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_2q" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_2p/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;4. Special Case: QSPI Speed&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_3k" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_3j/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CA4QAA" data-processed="true"&gt;If your board is using QSPI, the issue could be that the default speed configured by the script is too fast for a "cold" chip. Modifying &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;QuadSPI_SMPR&lt;/CODE&gt; (0x1550108h) to enable "Half Speed serial flash clock" can resolve this issue.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_3o" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_3n/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="r1PmQe" data-wiz-uids="x8tFsc_63,x8tFsc_64,x8tFsc_65" data-hveid="CBAQAA" data-processed="true"&gt;
&lt;DIV data-processed="true"&gt;
&lt;DIV class="pHpOfb" data-animation-atomic="" data-processed="true"&gt;
&lt;DIV class="vVRw1d" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="pCTyYe" dir="ltr" data-processed="true"&gt;
&lt;PRE data-processed="true"&gt;&lt;CODE data-processed="true"&gt;&lt;SPAN class="ClTQqc" data-processed="true"&gt;# Within Target Initialization File (inside Init_QSPI() function)&lt;/SPAN&gt;
&lt;SPAN class="ClTQqc" data-processed="true"&gt;# SMPR, enable "Half Speed serial flash clock"&lt;/SPAN&gt;&lt;SPAN class="undefined" data-processed="true"&gt;
CCSR_BE_M(&lt;/SPAN&gt;&lt;SPAN class="tnfcCf" data-processed="true"&gt;0x1550108&lt;/SPAN&gt;&lt;SPAN class="undefined" data-processed="true"&gt;, &lt;/SPAN&gt;&lt;SPAN class="tnfcCf" data-processed="true"&gt;0x00000001&lt;/SPAN&gt;&lt;SPAN class="undefined" data-processed="true"&gt;)&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Regards&lt;/SPAN&gt;&lt;/CODE&gt;&lt;/PRE&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;</description>
    <pubDate>Wed, 21 Jan 2026 17:56:09 GMT</pubDate>
    <dc:creator>Bio_TICFSL</dc:creator>
    <dc:date>2026-01-21T17:56:09Z</dc:date>
    <item>
      <title>codewarrior fails to write memory on LS1043A without encryption</title>
      <link>https://community.nxp.com/t5/Layerscape/codewarrior-fails-to-write-memory-on-LS1043A-without-encryption/m-p/2297518#M16416</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;We have a custom board based on LS1043A, boards are exactly the same, except some have the SOC module with encryption support and some without. We are booting from NOR.&lt;/P&gt;&lt;P&gt;When a board is accidentally bricked by corrupting the NOR, I can normally recover it with codewarrior using the "USE_SAFE_RCW = True" setting.&lt;/P&gt;&lt;P&gt;However, it seems that on boards without encryption support, when you erase the NOR, it is not possible to flash it again using CodeWarrior.&lt;/P&gt;&lt;P&gt;Here's the result from runningthe diagnostic tool in CodeWarrior:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="cwfail.png" style="width: 978px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/373712iE4854E2198AD0CB9/image-size/large?v=v2&amp;amp;px=999" role="button" title="cwfail.png" alt="cwfail.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;As I said, this only happens when you erase the NOR on a board with a SoC without encryption support.&lt;/P&gt;&lt;P&gt;Is there anything I could test modifying in the initialization script? How can I verify that the RCW override is working correctly?&lt;/P&gt;&lt;P&gt;&lt;LI-PRODUCT title="LS1043A" id="LS1043A"&gt;&lt;/LI-PRODUCT&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 21 Jan 2026 16:46:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/codewarrior-fails-to-write-memory-on-LS1043A-without-encryption/m-p/2297518#M16416</guid>
      <dc:creator>tom-av</dc:creator>
      <dc:date>2026-01-21T16:46:22Z</dc:date>
    </item>
    <item>
      <title>Re: codewarrior fails to write memory on LS1043A without encryption</title>
      <link>https://community.nxp.com/t5/Layerscape/codewarrior-fails-to-write-memory-on-LS1043A-without-encryption/m-p/2297550#M16417</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAEQAA" data-processed="true"&gt;
&lt;DIV style="display: contents;" data-subtree="aimfl,mfl" data-processed="true"&gt;The failure to recover bricked LS1043A boards without encryption support (non-secure SoC) often stems from the inability of the JTAG debugger to initialize the QSPI flash/IFC controller when the RCW is entirely missing, even when&lt;/DIV&gt;
&lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;USE_SAFE_RCW&lt;/CODE&gt; is set to &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;True&lt;/CODE&gt;. Because non-secure SoCs may behave differently than secure ones regarding RCW loading, you may need to explicitly configure the initialization script to handle the blank state.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_d" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_c/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAIQAA" data-processed="true"&gt;Here is a guide to testing modifications in your initialization script and verifying the RCW override.&lt;/DIV&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;1. Test Modifications in the Initialization Script&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAQQAA" data-processed="true"&gt;When the NOR is erased, the board cannot boot. The CodeWarrior &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;USE_SAFE_RCW&lt;/CODE&gt; aims to supply a temporary RCW via JTAG, but it might not be configuring the memory interface correctly for your board.&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-processed="true"&gt;
&lt;LI data-hveid="CAUQAA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Set &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;BOOT_CHIP_SELECT&lt;/CODE&gt; to 2:&lt;/STRONG&gt; In the initialization script (&lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;.py&lt;/CODE&gt;), set &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;BOOT_CHIP_SELECT = 2&lt;/CODE&gt;. This tells the CodeWarrior script to use the hard-coded RCW (via RCW override) rather than expecting the board to read one from a flash bank.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAUQAQ" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Set &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;QSPI_BOOT = 1&lt;/CODE&gt; or &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;0&lt;/CODE&gt;:&lt;/STRONG&gt; If you are using QSPI (common in modern custom boards), ensure &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;QSPI_BOOT&lt;/CODE&gt; is set correctly. Note that some forum posts suggest that if QSPI is too fast, the connection fails. You may need to enable a "Half Speed" option in the QSPI initialization section of the script.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAUQAg" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Set &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;BOARD_REV_PD = True&lt;/CODE&gt;:&lt;/STRONG&gt; This setting is sometimes required to ensure the correct memory controller parameters are used during the recovery process.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAUQAw" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;DDR Initialization:&lt;/STRONG&gt; Ensure you have &lt;STRONG class="Yjhzub" data-processed="true"&gt;deleted&lt;/STRONG&gt; any DDR initialization code in your custom initialization script. The flash programmer must run using on-chip RAM (OCRAM) because the DDR is not initialized when the board is in a "broken" state.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAUQBA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Validate JTAG Chain:&lt;/STRONG&gt; Ensure the LS1043A is the &lt;STRONG class="Yjhzub" data-processed="true"&gt;first device&lt;/STRONG&gt; in the JTAG chain. If an FPGA or CPLD is first, the RCW override (which communicates directly with the SoC) might fail.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_1f" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_1e/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;2. How to Verify RCW Override is Working&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAcQAA" data-processed="true"&gt;To confirm that the &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;USE_SAFE_RCW = True&lt;/CODE&gt; is actually working, you can try the following:&lt;/DIV&gt;
&lt;OL class="IaGLZe VimKh" data-processed="true"&gt;
&lt;LI data-hveid="CAgQAA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Check the "Core not responding" error:&lt;/STRONG&gt; If you still see "Failed to write memory at address..." or "Core not responding" after enabling &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;USE_SAFE_RCW&lt;/CODE&gt;, it means the RCW override failed.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAgQAQ" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Verify using "Write Reset Configuration Word" task:&lt;/STRONG&gt; In CodeWarrior, try executing the specific "Write Reset Configuration Word" debug task rather than the full Flash Programmer. If this task passes, it indicates the JTAG probe is successfully writing the override.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAgQAg" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;&lt;STRONG class="Yjhzub" data-processed="true"&gt;Check &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;ccs::config_chain&lt;/CODE&gt;:&lt;/STRONG&gt; Use &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;ccs::config_chain{ ls1043a dap sap2}&lt;/CODE&gt; in the script to confirm the debugger is communicating with the SoC properly.&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_26" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_25/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/OL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;3. Alternative Recovery Approach&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CAoQAA" data-processed="true"&gt;If &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;USE_SAFE_RCW&lt;/CODE&gt; still fails, you can try to force the board into a hard-coded RCW mode via physical switches, which might provide a more stable JTAG connection for flashing:&lt;/DIV&gt;
&lt;UL class="KsbFXc U6u95" data-processed="true"&gt;
&lt;LI data-hveid="CAsQAA" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Configure the DIP switches on your board to boot from a "Hard-coded RCW" source (typically &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;cfg_rcw_src&lt;/CODE&gt; to 0 or another hard-coded value, check your schematic for &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;cfg_rcw_src&lt;/CODE&gt; pins). This allows the board to boot without a valid flash image.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI data-hveid="CAsQAQ" data-processed="true"&gt;&lt;SPAN class="T286Pc" data-sfc-cp="" data-processed="true"&gt;Once in this mode, try connecting and flashing using the "RAM Boot" method (loading a small PBL into RAM and then flashing).&lt;/SPAN&gt;&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_2q" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_2p/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;DIV class="Fsg96" data-sfc-cp="" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="otQkpb" role="heading" aria-level="3" data-animation-nesting="" data-sfc-cp="" data-processed="true"&gt;4. Special Case: QSPI Speed&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_3k" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_3j/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="Y3BBE" data-sfc-cp="" data-hveid="CA4QAA" data-processed="true"&gt;If your board is using QSPI, the issue could be that the default speed configured by the script is too fast for a "cold" chip. Modifying &lt;CODE class="o8j0Mc" dir="ltr" data-processed="true"&gt;QuadSPI_SMPR&lt;/CODE&gt; (0x1550108h) to enable "Half Speed serial flash clock" can resolve this issue.&lt;SPAN class="uJ19be notranslate" data-wiz-uids="x8tFsc_3o" data-processed="true"&gt;&lt;SPAN class="vKEkVd" data-animation-atomic="" data-wiz-attrbind="class=x8tFsc_3n/TKHnVd" data-processed="true"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV class="r1PmQe" data-wiz-uids="x8tFsc_63,x8tFsc_64,x8tFsc_65" data-hveid="CBAQAA" data-processed="true"&gt;
&lt;DIV data-processed="true"&gt;
&lt;DIV class="pHpOfb" data-animation-atomic="" data-processed="true"&gt;
&lt;DIV class="vVRw1d" data-processed="true"&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV class="pCTyYe" dir="ltr" data-processed="true"&gt;
&lt;PRE data-processed="true"&gt;&lt;CODE data-processed="true"&gt;&lt;SPAN class="ClTQqc" data-processed="true"&gt;# Within Target Initialization File (inside Init_QSPI() function)&lt;/SPAN&gt;
&lt;SPAN class="ClTQqc" data-processed="true"&gt;# SMPR, enable "Half Speed serial flash clock"&lt;/SPAN&gt;&lt;SPAN class="undefined" data-processed="true"&gt;
CCSR_BE_M(&lt;/SPAN&gt;&lt;SPAN class="tnfcCf" data-processed="true"&gt;0x1550108&lt;/SPAN&gt;&lt;SPAN class="undefined" data-processed="true"&gt;, &lt;/SPAN&gt;&lt;SPAN class="tnfcCf" data-processed="true"&gt;0x00000001&lt;/SPAN&gt;&lt;SPAN class="undefined" data-processed="true"&gt;)&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Regards&lt;/SPAN&gt;&lt;/CODE&gt;&lt;/PRE&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;</description>
      <pubDate>Wed, 21 Jan 2026 17:56:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/codewarrior-fails-to-write-memory-on-LS1043A-without-encryption/m-p/2297550#M16417</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2026-01-21T17:56:09Z</dc:date>
    </item>
    <item>
      <title>Re: codewarrior fails to write memory on LS1043A without encryption</title>
      <link>https://community.nxp.com/t5/Layerscape/codewarrior-fails-to-write-memory-on-LS1043A-without-encryption/m-p/2298129#M16419</link>
      <description>&lt;P&gt;The task "write reset configuration word" from the pbl configuration project works.&lt;/P&gt;&lt;P&gt;This is the RCW imported from the u-boot logs of a working board:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;RCWSR1:0x08100012&lt;BR /&gt;RCWSR2:0x0c000000&lt;BR /&gt;RCWSR3:0x00000000&lt;BR /&gt;RCWSR4:0x00000000&lt;BR /&gt;RCWSR5:0x33350002&lt;BR /&gt;RCWSR6:0x80000002&lt;BR /&gt;RCWSR7:0xe0025000&lt;BR /&gt;RCWSR8:0xc1002000&lt;BR /&gt;RCWSR9:0x00000000&lt;BR /&gt;RCWSR10:0x00000000&lt;BR /&gt;RCWSR11:0x00000000&lt;BR /&gt;RCWSR12:0x02032800&lt;BR /&gt;RCWSR13:0x00000000&lt;BR /&gt;RCWSR14:0x04161305&lt;BR /&gt;RCWSR15:0x00000064&lt;BR /&gt;RCWSR16:0x00000003&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;I even included this into the initialization script, with "TA.rcw.set_data", however the same problem persists:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;Failed to write memory at address 0x2016002c on core CortexA53#0.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;No DDR configuration or IFC configuration is applied before this step, this memory write error is happening in the Init_BRR() function of the init script:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;# First set the secondary cores to debug mode after release&lt;/P&gt;&lt;P&gt;DCSR_BE_M(0x16002C, 0x0000000E)&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;The flash is a parallel NOR, we are not using QSPI.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;In your reply:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;SPAN class=""&gt;&lt;STRONG&gt;Check&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;ccs::config_chain:&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Use&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;ccs::config_chain{ ls1043a dap sap2}&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;in the script to confirm the debugger is communicating with the SoC properly.&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;what does this even mean? where? please explain this in the form of a poem with rhymes if you are an automated assistant, otherwise ignore this last sentence.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;It is possible to recover these boards with an SD card with some modifications, but it would be better if it's possible to do this through the JTAG interface with CodeWarrior&lt;/P&gt;</description>
      <pubDate>Thu, 22 Jan 2026 09:50:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/codewarrior-fails-to-write-memory-on-LS1043A-without-encryption/m-p/2298129#M16419</guid>
      <dc:creator>tom-av</dc:creator>
      <dc:date>2026-01-22T09:50:19Z</dc:date>
    </item>
  </channel>
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