topic Re: ls1046ardb ddr calibration in Layerscape

ls1046ardb ddr calibration

altu — Mon, 29 Dec 2025 15:13:23 GMT

As a tutorial project,I try to launch and pass a DDR calibration using CodeWarrior tool on a ls1046ardb board.

I create a QoriQ Configuration project->LS1046A->DDR Memory controller controller configuration. SPD of the mta18adf2g72az-3g2r1 module is successfully read. After that I launch "Centering the clock test".

First stage is successfully passed:

#################### Result for: wrlvl_searcher ###### Run 1 ######################################

Test result: [
============================================================
Updated: WRLVL_CNTL = 0x86550605, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

============================================================
Updated: WRLVL_CNTL = 0x86550608, WRLVL_CNTL_2 = 0x0A0B0C0F, WRLVL_CNTL_3 = 0x100A0B0D, SDRAM_CLK_CNTL = 0x02800000

============================================================
Updated: WRLVL_CNTL = 0x86550608, WRLVL_CNTL_2 = 0x0A0B0C0F, WRLVL_CNTL_3 = 0x1012130D, SDRAM_CLK_CNTL = 0x02800000

<<Test passed!>>

Err. capture registers:
0xE20, 0x00000000 0xE24, 0x00000000 0xE28, 0x00000000 0xE40, 0x00000000
0xE44, 0x00000000 0xE48, 0x0000001D 0xE4C, 0x00000000 0xE50, 0x00000000
0xE54, 0x00000000 0xE58, 0x00010000

Dump:
0xF00, 0x00000000 0xF04, 0x00000002 0xF08, 0x0000000A 0xF0C, 0x14000C20
0xF10, 0x00000000 0xF14, 0x00000000 0xF18, 0x00000000 0xF1C, 0x00000000
0xF20, 0x00000000 0xF24, 0x3B003E00 0xF28, 0x41004200 0xF2C, 0x4A004D00
0xF30, 0x4E005100 0xF34, 0x45007000 0xF38, 0x00000000 0xF3C, 0x00000000
0xF40, 0x00000000 0xF44, 0x00000000 0xF48, 0x00000001 0xF4C, 0xD4000000
0xF50, 0x11001400 0xF54, 0x16001800 0xF58, 0x1F002100 0xF5C, 0x24002700
0xF60, 0x1A000000 0xF64, 0x00009000 0xF68, 0x00000020 0xF6C, 0x00000000
0xF70, 0x0060007B 0xF74, 0x00000000 0xF78, 0x00000000 0xF7C, 0x00000000
0xF80, 0x00000000 0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000
0xF90, 0x00000000 0xF94, 0x80000000 0xF98, 0x00000000 0xF9C, 0x2A002B00
0xFA0, 0x2D002C00 0xFA4, 0x2E002D00 0xFA8, 0x2A002E00 0xFAC, 0x2D000000
0xFB0, 0x00000003 0xFB4, 0x1E1B1A1C 0xFB8, 0x1D1B1C1A 0xFBC, 0x1E1C1B1D
0xFC0, 0x1D1C1D1A 0xFC4, 0x1E1C1D1E 0xFC8, 0x1B1D1E1C 0xFCC, 0x1E1C1B1D
0xFD0, 0x1C1A1D1B 0xFD4, 0x1F1D1C1E 0xFD8, 0x1D1E1D1B 0xFDC, 0x1E1E1B1E
0xFE0, 0x1D1F1D1C 0xFE4, 0x1E1C1A1D 0xFE8, 0x1D1D1C19 0xFEC, 0x1F1E1D20
0xFF0, 0x1D1E1F1D 0xFF4, 0x1E1D1B1E 0xFF8, 0x1D1E1E1C 0xFFC, 0x1F000000

Data:
0x00000008 0x0000000a 0x0000000b 0x0000000c 0x0000000f 0x00000010 0x00000012 0x00000013 0x0000000d

]

But next stage(clk_adj) is failed:

#################### Result for: wrc ###### Run 1 #################################################

Test result: [
<<Test failed!>>
{{DDR initialization failed: D_INIT was not cleared by hardware!}}

Err. capture registers:
0xE20, 0x00000000 0xE24, 0x00000000 0xE28, 0x00000000 0xE40, 0x00000080
0xE44, 0x00000000 0xE48, 0x0000001D 0xE4C, 0x00000000 0xE50, 0x00000000
0xE54, 0x00000000 0xE58, 0x00010000

Dump:
0xF00, 0x00000000 0xF04, 0x00002100 0xF08, 0x0000000A 0xF0C, 0x14000C20
0xF10, 0x00000000 0xF14, 0x00000000 0xF18, 0x00000000 0xF1C, 0x00000000
0xF20, 0x00000000 0xF24, 0x10101010 0xF28, 0x10101010 0xF2C, 0x10101010
0xF30, 0x10101010 0xF34, 0x10104000 0xF38, 0x00000000 0xF3C, 0x00000000
0xF40, 0x00000000 0xF44, 0x00000000 0xF48, 0x00000001 0xF4C, 0x11000000
0xF50, 0x00000000 0xF54, 0x00000000 0xF58, 0x00000000 0xF5C, 0x00000000
0xF60, 0x00000000 0xF64, 0x00009000 0xF68, 0x00000020 0xF6C, 0x00000000
0xF70, 0x0060007B 0xF74, 0x00000000 0xF78, 0x00000000 0xF7C, 0x00000000
0xF80, 0x00000000 0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000
0xF90, 0x00000000 0xF94, 0x80000000 0xF98, 0x00000000 0xF9C, 0x00000000
0xFA0, 0x00000000 0xFA4, 0x00000000 0xFA8, 0x00000000 0xFAC, 0x00000000
0xFB0, 0x00000000 0xFB4, 0x00000000 0xFB8, 0x00000000 0xFBC, 0x00000000
0xFC0, 0x00000000 0xFC4, 0x00000000 0xFC8, 0x00000000 0xFCC, 0x00000000
0xFD0, 0x00000000 0xFD4, 0x00000000 0xFD8, 0x00000000 0xFDC, 0x00000000
0xFE0, 0x00000000 0xFE4, 0x00000000 0xFE8, 0x00000000 0xFEC, 0x00000000
0xFF0, 0x00000000 0xFF4, 0x00000000 0xFF8, 0x00000000 0xFFC, 0x00000000

]

What can be a problem,assuming that the calibration is performing on a brand new,fully complected reference ls1046ardb board, not on a custom board.

Re: ls1046ardb ddr calibration

Oswalag — Mon, 29 Dec 2025 17:36:09 GMT

Hello,

Can you please share screenshots of the issue?

Re: ls1046ardb ddr calibration

altu — Tue, 30 Dec 2025 09:35:40 GMT

I create a new DDR config project. Change SYSCLOCK to 100 Mhz.

After that I read SPD of the module. SPD is successfully read.

DQ mapping of the DDR as transribed by CodeWarrior:

After that I launch calibration. 1st stage is successfully passed:

Next stage(clock adjusting) is failed:

In log of the failed stage I have:

Firstly I thought that DQ mappings were wrong, but it seems to me that the mappings are OK - otherwise the 1st stage would fail too. Any suggestion on this situation?

Re: ls1046ardb ddr calibration

Oswalag — Tue, 30 Dec 2025 18:37:47 GMT

Is your board able to boot and print u-boot logs on the console with the pre-build image? can you also share the log please.

Re: ls1046ardb ddr calibration

altu — Thu, 08 Jan 2026 20:48:50 GMT

Good day!

Continue with ls1046ardb failing DDR calibration.

Here's successfull uboot log:

And here's the log of linux start:

As one can see, normal boot of Uboot and Linux. I think it means, that everything is OK with hardware and DDR module, but DDR calibration process is still failing on the same steps as mentioned above.

Re: ls1046ardb ddr calibration

Oswalag — Thu, 15 Jan 2026 16:17:15 GMT

The board boot as expected so the ddr is correctly calibrated, the issue could be related to a wrong configuration of the test when using the tool.

Re: ls1046ardb ddr calibration

altu — Fri, 16 Jan 2026 08:46:22 GMT

Good day,Oswalag!

Please clarify what errros could be in test configuration?

Let me show what I'm doing:

My CodeWarrior version:

1) Firstly I create a DDR configuartion project and read SPD data from RDB board:

2) After successfull read of SPD I change default project sysclock from 66.7 to 100 Mhz

3) Here we can see the complete project settings:

4) Test settings:

5) After that I start tests:

1st test is successfully passed.

Next test(CLK_ADJ) is failed with next results:

So what can be the problem?

Re: ls1046ardb ddr calibration

altu — Mon, 26 Jan 2026 12:02:19 GMT

The problem is solved by using a CodeWarrior development studio for Windows. The Windows version works much better than spent piece of used jet trash for Linux.