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    <title>topic Using EDMA for PCIE in lS1043A in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/Using-EDMA-for-PCIE-in-lS1043A/m-p/2197962#M16267</link>
    <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;we are using 3 instances of Pcie in our system. as per our system needs we need to use DMA. we needs to know how to enable the DMA.&amp;nbsp;&lt;/P&gt;&lt;P&gt;how to enable? whether it needs to be added on Device tree or how it needs to be done?&lt;/P&gt;&lt;P&gt;we are usinf ls1043ardb board and we are using yocto-real-time-edge BSP,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;i have checked device tree and there is no dma-ranges mentioned under any of the Pcie nodes.&lt;/P&gt;&lt;P&gt;below is the device tree under fsl-ls1043a.dtsi&lt;/P&gt;&lt;P&gt;"pcie1: pcie@3400000 {&lt;BR /&gt;compatible = "fsl,ls1043a-pcie";&lt;BR /&gt;reg = &amp;lt;0x00 0x03400000 0x0 0x00100000&amp;gt;, /* controller registers */&lt;BR /&gt;&amp;lt;0x40 0x00000000 0x0 0x00002000&amp;gt;; /* configuration space */&lt;BR /&gt;reg-names = "regs", "config";&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;interrupt-names = "pme", "aer";&lt;BR /&gt;#address-cells = &amp;lt;3&amp;gt;;&lt;BR /&gt;#size-cells = &amp;lt;2&amp;gt;;&lt;BR /&gt;device_type = "pci";&lt;BR /&gt;iommu-map = &amp;lt;0 &amp;amp;smmu 0 1&amp;gt;; /* update by bootloader */&lt;BR /&gt;num-viewport = &amp;lt;6&amp;gt;;&lt;BR /&gt;bus-range = &amp;lt;0x0 0xff&amp;gt;;&lt;BR /&gt;ranges = &amp;lt;0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */&lt;BR /&gt;0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000&amp;gt;; /* non-prefetchable memory */&lt;BR /&gt;msi-parent = &amp;lt;&amp;amp;msi1&amp;gt;, &amp;lt;&amp;amp;msi2&amp;gt;, &amp;lt;&amp;amp;msi3&amp;gt;;&lt;BR /&gt;#interrupt-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;interrupt-map-mask = &amp;lt;0 0 0 7&amp;gt;;&lt;BR /&gt;interrupt-map = &amp;lt;0000 0 0 1 &amp;amp;gic 0 110 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 2 &amp;amp;gic 0 111 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 3 &amp;amp;gic 0 112 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 4 &amp;amp;gic 0 113 0x4&amp;gt;;&lt;BR /&gt;fsl,pcie-scfg = &amp;lt;&amp;amp;scfg 0&amp;gt;;&lt;BR /&gt;big-endian;&lt;BR /&gt;status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;pcie2: pcie@3500000 {&lt;BR /&gt;compatible = "fsl,ls1043a-pcie";&lt;BR /&gt;reg = &amp;lt;0x00 0x03500000 0x0 0x00100000&amp;gt;, /* controller registers */&lt;BR /&gt;&amp;lt;0x48 0x00000000 0x0 0x00002000&amp;gt;; /* configuration space */&lt;BR /&gt;reg-names = "regs", "config";&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;interrupt-names = "pme", "aer";&lt;BR /&gt;#address-cells = &amp;lt;3&amp;gt;;&lt;BR /&gt;#size-cells = &amp;lt;2&amp;gt;;&lt;BR /&gt;device_type = "pci";&lt;BR /&gt;iommu-map = &amp;lt;0 &amp;amp;smmu 0 1&amp;gt;; /* update by bootloader */&lt;BR /&gt;num-viewport = &amp;lt;6&amp;gt;;&lt;BR /&gt;bus-range = &amp;lt;0x0 0xff&amp;gt;;&lt;BR /&gt;ranges = &amp;lt;0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */&lt;BR /&gt;0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000&amp;gt;; /* non-prefetchable memory */&lt;BR /&gt;msi-parent = &amp;lt;&amp;amp;msi1&amp;gt;, &amp;lt;&amp;amp;msi2&amp;gt;, &amp;lt;&amp;amp;msi3&amp;gt;;&lt;BR /&gt;#interrupt-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;interrupt-map-mask = &amp;lt;0 0 0 7&amp;gt;;&lt;BR /&gt;interrupt-map = &amp;lt;0000 0 0 1 &amp;amp;gic 0 120 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 2 &amp;amp;gic 0 121 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 3 &amp;amp;gic 0 122 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 4 &amp;amp;gic 0 123 0x4&amp;gt;;&lt;BR /&gt;fsl,pcie-scfg = &amp;lt;&amp;amp;scfg 1&amp;gt;;&lt;BR /&gt;big-endian;&lt;BR /&gt;status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;pcie3: pcie@3600000 {&lt;BR /&gt;compatible = "fsl,ls1043a-pcie";&lt;BR /&gt;reg = &amp;lt;0x00 0x03600000 0x0 0x00100000&amp;gt;, /* controller registers */&lt;BR /&gt;&amp;lt;0x50 0x00000000 0x0 0x00002000&amp;gt;; /* configuration space */&lt;BR /&gt;reg-names = "regs", "config";&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;interrupt-names = "pme", "aer";&lt;BR /&gt;#address-cells = &amp;lt;3&amp;gt;;&lt;BR /&gt;#size-cells = &amp;lt;2&amp;gt;;&lt;BR /&gt;device_type = "pci";&lt;BR /&gt;iommu-map = &amp;lt;0 &amp;amp;smmu 0 1&amp;gt;; /* update by bootloader */&lt;BR /&gt;num-viewport = &amp;lt;6&amp;gt;;&lt;BR /&gt;bus-range = &amp;lt;0x0 0xff&amp;gt;;&lt;BR /&gt;ranges = &amp;lt;0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */&lt;BR /&gt;0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000&amp;gt;; /* non-prefetchable memory */&lt;BR /&gt;msi-parent = &amp;lt;&amp;amp;msi1&amp;gt;, &amp;lt;&amp;amp;msi2&amp;gt;, &amp;lt;&amp;amp;msi3&amp;gt;;&lt;BR /&gt;#interrupt-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;interrupt-map-mask = &amp;lt;0 0 0 7&amp;gt;;&lt;BR /&gt;interrupt-map = &amp;lt;0000 0 0 1 &amp;amp;gic 0 154 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 2 &amp;amp;gic 0 155 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 3 &amp;amp;gic 0 156 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 4 &amp;amp;gic 0 157 0x4&amp;gt;;&lt;BR /&gt;fsl,pcie-scfg = &amp;lt;&amp;amp;scfg 2&amp;gt;;&lt;BR /&gt;big-endian;&lt;BR /&gt;status = "okay";&lt;BR /&gt;}; "&lt;/P&gt;&lt;P&gt;so let me know how to do it.&lt;/P&gt;&lt;P&gt;#ls1043a&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Tue, 04 Nov 2025 04:50:53 GMT</pubDate>
    <dc:creator>Naveenkumar_Muthusamy</dc:creator>
    <dc:date>2025-11-04T04:50:53Z</dc:date>
    <item>
      <title>Using EDMA for PCIE in lS1043A</title>
      <link>https://community.nxp.com/t5/Layerscape/Using-EDMA-for-PCIE-in-lS1043A/m-p/2197962#M16267</link>
      <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;we are using 3 instances of Pcie in our system. as per our system needs we need to use DMA. we needs to know how to enable the DMA.&amp;nbsp;&lt;/P&gt;&lt;P&gt;how to enable? whether it needs to be added on Device tree or how it needs to be done?&lt;/P&gt;&lt;P&gt;we are usinf ls1043ardb board and we are using yocto-real-time-edge BSP,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;i have checked device tree and there is no dma-ranges mentioned under any of the Pcie nodes.&lt;/P&gt;&lt;P&gt;below is the device tree under fsl-ls1043a.dtsi&lt;/P&gt;&lt;P&gt;"pcie1: pcie@3400000 {&lt;BR /&gt;compatible = "fsl,ls1043a-pcie";&lt;BR /&gt;reg = &amp;lt;0x00 0x03400000 0x0 0x00100000&amp;gt;, /* controller registers */&lt;BR /&gt;&amp;lt;0x40 0x00000000 0x0 0x00002000&amp;gt;; /* configuration space */&lt;BR /&gt;reg-names = "regs", "config";&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;lt;GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;interrupt-names = "pme", "aer";&lt;BR /&gt;#address-cells = &amp;lt;3&amp;gt;;&lt;BR /&gt;#size-cells = &amp;lt;2&amp;gt;;&lt;BR /&gt;device_type = "pci";&lt;BR /&gt;iommu-map = &amp;lt;0 &amp;amp;smmu 0 1&amp;gt;; /* update by bootloader */&lt;BR /&gt;num-viewport = &amp;lt;6&amp;gt;;&lt;BR /&gt;bus-range = &amp;lt;0x0 0xff&amp;gt;;&lt;BR /&gt;ranges = &amp;lt;0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */&lt;BR /&gt;0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000&amp;gt;; /* non-prefetchable memory */&lt;BR /&gt;msi-parent = &amp;lt;&amp;amp;msi1&amp;gt;, &amp;lt;&amp;amp;msi2&amp;gt;, &amp;lt;&amp;amp;msi3&amp;gt;;&lt;BR /&gt;#interrupt-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;interrupt-map-mask = &amp;lt;0 0 0 7&amp;gt;;&lt;BR /&gt;interrupt-map = &amp;lt;0000 0 0 1 &amp;amp;gic 0 110 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 2 &amp;amp;gic 0 111 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 3 &amp;amp;gic 0 112 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 4 &amp;amp;gic 0 113 0x4&amp;gt;;&lt;BR /&gt;fsl,pcie-scfg = &amp;lt;&amp;amp;scfg 0&amp;gt;;&lt;BR /&gt;big-endian;&lt;BR /&gt;status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;pcie2: pcie@3500000 {&lt;BR /&gt;compatible = "fsl,ls1043a-pcie";&lt;BR /&gt;reg = &amp;lt;0x00 0x03500000 0x0 0x00100000&amp;gt;, /* controller registers */&lt;BR /&gt;&amp;lt;0x48 0x00000000 0x0 0x00002000&amp;gt;; /* configuration space */&lt;BR /&gt;reg-names = "regs", "config";&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;lt;GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;interrupt-names = "pme", "aer";&lt;BR /&gt;#address-cells = &amp;lt;3&amp;gt;;&lt;BR /&gt;#size-cells = &amp;lt;2&amp;gt;;&lt;BR /&gt;device_type = "pci";&lt;BR /&gt;iommu-map = &amp;lt;0 &amp;amp;smmu 0 1&amp;gt;; /* update by bootloader */&lt;BR /&gt;num-viewport = &amp;lt;6&amp;gt;;&lt;BR /&gt;bus-range = &amp;lt;0x0 0xff&amp;gt;;&lt;BR /&gt;ranges = &amp;lt;0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */&lt;BR /&gt;0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000&amp;gt;; /* non-prefetchable memory */&lt;BR /&gt;msi-parent = &amp;lt;&amp;amp;msi1&amp;gt;, &amp;lt;&amp;amp;msi2&amp;gt;, &amp;lt;&amp;amp;msi3&amp;gt;;&lt;BR /&gt;#interrupt-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;interrupt-map-mask = &amp;lt;0 0 0 7&amp;gt;;&lt;BR /&gt;interrupt-map = &amp;lt;0000 0 0 1 &amp;amp;gic 0 120 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 2 &amp;amp;gic 0 121 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 3 &amp;amp;gic 0 122 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 4 &amp;amp;gic 0 123 0x4&amp;gt;;&lt;BR /&gt;fsl,pcie-scfg = &amp;lt;&amp;amp;scfg 1&amp;gt;;&lt;BR /&gt;big-endian;&lt;BR /&gt;status = "okay";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;pcie3: pcie@3600000 {&lt;BR /&gt;compatible = "fsl,ls1043a-pcie";&lt;BR /&gt;reg = &amp;lt;0x00 0x03600000 0x0 0x00100000&amp;gt;, /* controller registers */&lt;BR /&gt;&amp;lt;0x50 0x00000000 0x0 0x00002000&amp;gt;; /* configuration space */&lt;BR /&gt;reg-names = "regs", "config";&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH&amp;gt;,&lt;BR /&gt;&amp;lt;GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;interrupt-names = "pme", "aer";&lt;BR /&gt;#address-cells = &amp;lt;3&amp;gt;;&lt;BR /&gt;#size-cells = &amp;lt;2&amp;gt;;&lt;BR /&gt;device_type = "pci";&lt;BR /&gt;iommu-map = &amp;lt;0 &amp;amp;smmu 0 1&amp;gt;; /* update by bootloader */&lt;BR /&gt;num-viewport = &amp;lt;6&amp;gt;;&lt;BR /&gt;bus-range = &amp;lt;0x0 0xff&amp;gt;;&lt;BR /&gt;ranges = &amp;lt;0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */&lt;BR /&gt;0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000&amp;gt;; /* non-prefetchable memory */&lt;BR /&gt;msi-parent = &amp;lt;&amp;amp;msi1&amp;gt;, &amp;lt;&amp;amp;msi2&amp;gt;, &amp;lt;&amp;amp;msi3&amp;gt;;&lt;BR /&gt;#interrupt-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;interrupt-map-mask = &amp;lt;0 0 0 7&amp;gt;;&lt;BR /&gt;interrupt-map = &amp;lt;0000 0 0 1 &amp;amp;gic 0 154 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 2 &amp;amp;gic 0 155 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 3 &amp;amp;gic 0 156 0x4&amp;gt;,&lt;BR /&gt;&amp;lt;0000 0 0 4 &amp;amp;gic 0 157 0x4&amp;gt;;&lt;BR /&gt;fsl,pcie-scfg = &amp;lt;&amp;amp;scfg 2&amp;gt;;&lt;BR /&gt;big-endian;&lt;BR /&gt;status = "okay";&lt;BR /&gt;}; "&lt;/P&gt;&lt;P&gt;so let me know how to do it.&lt;/P&gt;&lt;P&gt;#ls1043a&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 04 Nov 2025 04:50:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Using-EDMA-for-PCIE-in-lS1043A/m-p/2197962#M16267</guid>
      <dc:creator>Naveenkumar_Muthusamy</dc:creator>
      <dc:date>2025-11-04T04:50:53Z</dc:date>
    </item>
    <item>
      <title>Re: Using EDMA for PCIE in lS1043A</title>
      <link>https://community.nxp.com/t5/Layerscape/Using-EDMA-for-PCIE-in-lS1043A/m-p/2212045#M16300</link>
      <description>&lt;P&gt;dear&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/208109"&gt;@Naveenkumar_Muthusamy&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The apps team has sent the below information:&lt;/P&gt;
&lt;P&gt;For qDMA on ls1043a, there is no need to add a DMA range in pcie node, only the qDMA node in device tree is required.&lt;BR /&gt;To enable qDMA, refer to LSDKUG Chapter 7.2.11 "QDMA for platform with DPAA1" part for the necessary kernel configuration.&lt;BR /&gt;The customer can enable CONFIG_DMATEST=y and use the kernel dmatest to verify qDMA functionality. By default, the test performs memory-to-memory transfers. The test commands can be found in Chapter 7.2.11. &lt;BR /&gt;I will provide a patch for memory-to-pcie testing. Note the patch version may differ from the customer's kernel, so they need to port it accordingly. The user must assign a pcie physical address to qDMA, then qDMA will transfer the data from memory to pcie. From a DMA perspective, there is no difference between memory and pcie -- they are both treated as physical addresses.&lt;BR /&gt;The below commands are needed for memory-to-pcie transfer:&lt;BR /&gt;echo 0x4841800000 &amp;gt; /sys/module/dmatest/parameters/pci_phys_addr # need change to customer's pcie address&lt;BR /&gt;echo 1 &amp;gt; /sys/module/dmatest/parameters/dmatest_pcie&lt;BR /&gt;Then, follow the test procedure described in Chapter 7.2.11.&lt;BR /&gt;Once the test passes, the customer can refer to the interface usage in dmatest.c and integrated relevant code into their files.&lt;/P&gt;
&lt;P&gt;review the attached file please.&lt;/P&gt;
&lt;P&gt;BR&lt;/P&gt;
&lt;P&gt;LFGP&lt;/P&gt;</description>
      <pubDate>Wed, 19 Nov 2025 16:10:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Using-EDMA-for-PCIE-in-lS1043A/m-p/2212045#M16300</guid>
      <dc:creator>LFGP</dc:creator>
      <dc:date>2025-11-19T16:10:12Z</dc:date>
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