topic Re: LS1028A + RGMII TX_CLK not working in Layerscape

LS1028A + RGMII TX_CLK not working

Allen_C_Kim — Sat, 25 Oct 2025 04:08:19 GMT

I'm working on a custom board (#LS1028A) with RGMII PHY Chip.

The custom board is booting well, but the problem is that the TX_CLK from the CPU is not being generated. I have double-checked the RCW and U-Boot, which have no errors.

In RCW,

EC1_SAI4_5_PMUX=0

EC1_SAI3_6_PMUX=0

GTX_CLK125_PMUX = 0

And, U-Boot DTS

&enetc_port1 {

status = "okay";

phy-mode = "rgmii-id";

phy-handle = <&rgmii_phy0>;

};

&enetc_mdio_pf3 {

status = "okay";

rgmii_phy0: ethernet-phy@0 {

reg = <0x0>;

compatible="ethernet-phy-id2000.a231";

ti,rx-internal-delay = <0x8>;

ti,tx-internal-delay = <0xa>;

ti,fifo-depth = <0x1>;

};

---

In U-Boot, when I use a ping command, there is no TX_CLK signal, which I measured using an oscilloscope.

When I ping from the outside, using my development PC, the U-Boot showed that it received an ARP request message, and it sent an ARP-Reply which was not transmitted.

I searched the community, but I couldn't find any useful information.

What should I do next?

Thanks in advance,

Re: LS1028A + RGMII TX_CLK not working

June_Lu — Wed, 29 Oct 2025 03:40:50 GMT

have you excluded the soldering issue?

Thanks

Re: LS1028A + RGMII TX_CLK not working

Allen_C_Kim — Wed, 29 Oct 2025 07:52:25 GMT

We already checked that soldering status. There is no problem!

Re: LS1028A + RGMII TX_CLK not working

June_Lu — Thu, 30 Oct 2025 01:49:15 GMT

would you kindly share your this par schematics to check? thanks

Re: LS1028A + RGMII TX_CLK not working

Allen_C_Kim — Thu, 30 Oct 2025 04:56:48 GMT

@June_Lu,

I attached the RGMII part schematic.

Thanks...

Re: LS1028A + RGMII TX_CLK not working

June_Lu — Fri, 31 Oct 2025 03:10:04 GMT

Working with the AE team now. Will update later.

Re: LS1028A + RGMII TX_CLK not working

June_Lu — Fri, 31 Oct 2025 10:26:10 GMT

For RGMII, you can refer to fsl-ls1028a-qds.dts and below patch attached.

You can also check the following register:

— RGMII mode: This mode is enabled by setting port MAC register IF_MODE[IFMODE] to b10, IF_MODE[RG] to 1'b1. Link speed is either automatically configured by setting IF_MODE[ENA] to 1, or manually configured by IF_MODE[SSP] when ENA bit is 0. For RGMII internal loopback mode, set IF_MODE[RLP] to b1.

Re: LS1028A + RGMII TX_CLK not working

Allen_C_Kim — Sun, 02 Nov 2025 00:09:35 GMT

Thanks for your reply,

I've already checked that the fsl-ls1028a-qds.dts and configured my DTS as it said. And the RGMII Mode configuration you mentioned is already in U-Boot, and I have verified it using "md" command.

I also performed the Loopback test in RGMII, and it worked fine. I tested the loopback mode with a Ping command in Uboot.

Re: LS1028A + RGMII TX_CLK not working

Allen_C_Kim — Mon, 03 Nov 2025 07:31:12 GMT

I have some questions related to RGMII in LS1028A.

1. RGMII Block Diagram

I looked through the LS1028A RM document, but I could not find the RGMII block diagram. May I ask you to give me the RGMII block diagram of LS1028A if available?

2. RGMII-related Register

Besides RCW, the ENETC Port Station Interface registers, and ENETC base/physical function registers, are there any registers related to RGMII? In other CPUs, there are clock-gating and power-down registers that can control the clock and power of a given peripheral. Does LS1028A provide such a functionality?

3. GTX_CLK generation

I wonder if I provide a 125MHz clock to EC1_GTX_CLK125, the EC1_GTX_CLK will be generated automatically if I set the related registers correctly? Are there any conditions for generating EC1_GTX_CLK?

I hope I get the responses as soon as possible.

Thanks,

Re: LS1028A + RGMII TX_CLK not working

June_Lu — Mon, 03 Nov 2025 13:42:54 GMT

Please also share you RCW file and register dump.

Thanks

Re: LS1028A + RGMII TX_CLK not working

June_Lu — Tue, 04 Nov 2025 13:49:11 GMT

You can refer to the attached block diagram.

About configuration of registers, I think they are same with sgmii. don't like i.MX CPUs, layerscape series have no clock-gating/power down registers.

If providing a 125MHz clock to EC1_GTX_CLK125, I think the EC1_GTX_CLK will be generated automatically.

however if you plan to use 125M clock input from PHY chip, you need enable CLK_OUT signal of PHY.

Now you provide the 125MHz clock into the EC1_GTX_CLK125, but the

EC1_GTX_CLK125 belong to the OVDD power domain, it should be 1.8V instead of 3.3V. Check the Y4 clock output voltage first.

Thanks

Re: LS1028A + RGMII TX_CLK not working

Allen_C_Kim — Wed, 05 Nov 2025 00:09:24 GMT

Dear June Lu,

What I asked for was not a RGMII-PHY interconnection diagram, but the internal block diagram of RGMII in the LS1028A.

We already found the mistake in the OSC power and revised it to use the 1.8V.

So, in your opinion, if we provide the 125MHz clock to EC1_GTX_CLK125, the EC1_GTX_CLK will be generated automatically, right?

And, I am glad to know that the layerscape does not provide clock-gating/power-down register.

What should I do next? What kind of thing should I check out?

Thanks,

Re: LS1028A + RGMII TX_CLK not working

Allen_C_Kim — Sat, 08 Nov 2025 01:52:54 GMT

I found the solution to this problem. The problem is that the TX_CLK signal line is shorted to GND. We revised the PCB, and the Ethernet is working.

Thanks for your support.

Re: LS1028A + RGMII TX_CLK not working

June_Lu — Mon, 10 Nov 2025 03:16:30 GMT

Thanks for sharing the result, that's great.