LayerscapeのトピックRe: Clarification on erratum

Clarification on erratum

rhaas — Fri, 10 Oct 2025 15:55:23 GMT

I have been reviewing A-008822 in the LS1028A errata (LS1028ACE, Rev2, 2/2023). In A-008822, the workaround asks for a write to the PCIe configurations space offset 8D0h to occur.

I looked in the LS1028A TRM and I was not able to find this register listed.

Is it possible to get the definition of this register. I would like to understand the workaround; in case someone asks.

Re: Clarification on erratum

Oswalag — Tue, 14 Oct 2025 22:21:16 GMT

Hello,

There isn't a public description of the register available.

Wording of the erratum A-008822 describes the issue in detail.
As stated, that workaround changes AXI slave response for all error scenarios on non-posted requests from default OKAY to ERROR.

Additional details cannot be provided to the customer because the PCIe IP internals are confidential.

Regards.

Re: Clarification on erratum

rhaas — Thu, 16 Oct 2025 13:01:11 GMT

Thank you for the information.

I was wondering if any 'write enable' bit needs to be set before writing this data, similar to MISC_CONTROL_1_OFF.

Thank you