Layerscape中的主题 Re: LX2080

LX2080

YY2410 — Mon, 29 Sep 2025 07:05:43 GMT

怀疑 LX2080 处理器在低温环境下通过 Norflash（NOR 闪存）加载时存在时序异常，该如何在预启动加载器（Pre-Boot Loader，简称 PBL）阶段修改 Flex SPI（灵活串行外设接口）的总线宽度、频率、时序等配置？应参考哪份文档？默认启动采用单总线加载方式 —— 切换为多总线加载能否改善该情况？

It is suspected that the LX2080 processor has timing abnormalities when loading via Norflash (NOR Flash Memory) in a low-temperature environment. How to modify the configuration of bus width, frequency, timing, etc. of Flex SPI (Flexible Serial Peripheral Interface) during the Pre-Boot Loader (PBL for short) phase? Which document should be referenced? The default startup uses a single-bus loading method—can switching to multi-bus loading improve this situation?

Re: LX2080

June_Lu — Mon, 29 Sep 2025 10:52:28 GMT

刚开始时, RCW 是靠内部的bootROM加载的，默认的分频值是80，分频器件的输入时钟是system clock。如果您的system clock是100M，频率是12.5M.

PBI加载阶段也无法更改这个时钟，最早可更改在PBI中，例如：

https://github.com/nxp-qoriq/rcw/blob/45e69253690452656a4dfe933c4c9f55e1eb0f5f/lx2160ardb_rev2/XGGFF_PP_HHHH_RR_19_5_2/rcw_2200_750_3200_19_5_2.rcw#L53

如果想更改宽度，也可以尝试在此设置flexSPI的LUT, 可以参考QSPI的文档.

Configure QSPI Bus Width and Frequency in Pre-Boot Loader Stage on LS Series Processors Application Note

如果是低温造成的不稳定，建议找到根本原因。因为在RCW加载阶段已经是单bit以及最慢分频时钟了。

Re: LX2080

YY2410 — Tue, 30 Sep 2025 09:33:12 GMT

收到，谢谢