LayerscapeのトピックRe: Serdes PLL RST_ERR on LS1028A

Serdes PLL RST_ERR on LS1028A

pb3 — Wed, 10 Sep 2025 12:40:05 GMT

Hi I've been working on a custom board based on LS1027A.

I've managed to bring up all software stack including Linux.

Now I'm trying to bring-up the Serdes. Initially during the bring-up phase I had to disable both PLL's because due to the PLL lock error the reset req was triggered.

Now I need to face it again.

The thing is that I use the same configuration for Serdes protocols as on LS1028ARDB.

The problem is that I constantly get RST_ERR in SerDes PLLa Reset Control Register thus board keeps reseting.

What can be the reason why it happens? Where to start debugging? What should I check?

Re: Serdes PLL RST_ERR on LS1028A

pb3 — Wed, 10 Sep 2025 12:43:07 GMT

Here's my RCW config

/*
* SerDes Protocol - 0x85bb
*
* Frequencies:
* Core -- 1500 MHz
* Platform -- 400 MHz
* DDR -- 1600 MHz
* DDR Data Rate -- 1.600 GT/s
*/

#include <../ls1028asi/ls1028a.rcwi>

SYS_PLL_RAT=4
MEM_PLL_RAT=16
CGA_PLL1_RAT=15
CGA_PLL2_RAT=12
HWA_CGA_M1_CLK_SEL=3
HWA_CGA_M2_CLK_SEL=7
HWA_CGA_M3_CLK_SEL=6
HWA_CGA_M4_CLK_SEL=3
DDR_REFCLK_SEL=2
DRAM_LAT=1
BOOT_LOC=21
FLASH_CFG1=3
SYSCLK_FREQ=600
IIC2_PMUX=6
IIC4_PMUX=2
IIC6_PMUX=3
XSPI1_A_DATA74_PMUX=1
CLK_OUT_PMUX=2
USB3_CLK_FSEL=39
ENETC_RCW=3
SRDS_PRTCL_S1_L0=8
SRDS_PRTCL_S1_L1=5
SRDS_PRTCL_S1_L2=11
SRDS_PRTCL_S1_L3=11

/* Added DDR tests */
SRDS_PLL_PD_PLL1=0
SRDS_PLL_PD_PLL2=0

/* Errata for PCIe controller */
#include <../ls1028asi/a008851.rcw>
#include <../ls1028asi/a010477.rcw>
#include <../ls1028asi/a009531.rcw>

/* Increase FSPI clock frequency */
#include <../ls1028asi/fspi_speed.rcw>

Re: Serdes PLL RST_ERR on LS1028A

LFGP — Wed, 10 Sep 2025 17:10:15 GMT

Dear @pb3,

""Up to 1.5 GHz operation""
your sys_clk is set to 600MHz and the SYS_PLL_RAT = 4 , so you are trying to operate at 2.4GHz
You must set the SYSCLK_FREQ = 100
review the "4.8.8.7 Reset Control Word (RCW) Register Descriptions" in the reference manual.

BR
LFGP

Re: Serdes PLL RST_ERR on LS1028A

pb3 — Wed, 10 Sep 2025 17:54:05 GMT

Are you sure about this? This is excatly the same setting as on LS1028A-RDB https://github.com/nxp-qoriq/rcw/blob/master/ls1028ardb/R_SQPP_0x85bb/rcw_1500_sdboot.rcw

It also has SYSCLK_FREQ=600 and SYS_PLL_RAT = 4.
What's more according to LS1028A Refernce Manual, 4.8.8 the only valid option for SYSCLK_FREQ is 0b1001011000
600 (decimal like in RCW) = 0b1001011000 so I think that's not the problem here.

Re: Serdes PLL RST_ERR on LS1028A

LFGP — Thu, 11 Sep 2025 01:53:48 GMT

Dear @pb3,
you are right, sorry for my mistake.
SRDS_PLL_PD_PLLx>> "SerDes PLLs are powered up in the POR Reset state
titled "SERDES Released from Reset".
If this field is set to 0, it informs RESET_REQ logic that
it should assert RESET_REQ if a proper reference clock
isn't applied or the SERDES PLL does not lock."
With this in mind, you need to check the system clock (with an oscilloscope) to discard some an inestable signal.

on the other hand, please set the SYS_PLL_SPD = 0 and set the SYS_PLL_RAT = 5

please let me know the results.
best regards
LFGP

Re: Serdes PLL RST_ERR on LS1028A

pb3 — Thu, 11 Sep 2025 10:13:33 GMT

Sorry, but I have a slight feeling that your answers are kinda random. My SYS_PLL_SPD is already set to 0 and SYS_PLL_RAT = 5 is an invalid value.

Re: Serdes PLL RST_ERR on LS1028A

LFGP — Thu, 11 Sep 2025 16:54:43 GMT

Dear @pb3,
could you please share with me the logs (I had to disable both PLL's, and with PLL enabled).
Also, please let me know the complete part number of the LS1027a you are using, please share a picture of the device.
Please double check if there is an stable signal to 100MHz:
DIFF_SYSCLK/ DIFF_SYSCLK_B ------>>>> These pins are the differential primary clock input to the chip and support ""100 MHz only"".
There is an issue reported in the "Chip errata", that could be related to your issue.
>>>>>>>>>>>>>
Workaround
• With platform frequency is equal to 300 MHz
— For normal operations, use IP command mode
— Use I2C, SD, or eMMC as a boot source.
• OR use platform frequency equal to 400 MHz and CPU speed equal to 1500/1300/1000 MHz. Do not use part number
with "CPU Speed" = 'H'. (refer Table 'Part numbering nomenclature' in the datasheet).
<<<<<<<<<<<<<<<<

best regards
LFGP

Re: Serdes PLL RST_ERR on LS1028A

LFGP — Thu, 11 Sep 2025 17:00:25 GMT

you could try the next workaround:
>>Once STS2[AREFLOCK, ASLVLOCK] bit for channel A (or STS2[BREFLOCK, BSLVLOCK] bit for channel B) is set to one, insert a delay of 4 μs before use of FlexSPI.
<<

Re: Serdes PLL RST_ERR on LS1028A

pb3 — Fri, 12 Sep 2025 09:09:57 GMT

Are we talking about the same? Why did you even mention FlexSPI that I'm not using at all? I don't want to be rude but if you don't know the topic - that's fine, just please assign someone else to have a look at this.

I have a problem with SERDES PLL not locking and as a result it constantly tries to recover by asserting RESET_REQ, in both PLL1RSTCTL and PLL2RSTCTL I have RST_ERR bit set indicating that (according to the manual) - "1b - PLL lock didn't happen in the expected time period"

SD1_REF_CLK1_P/N = 100MHz
SD1_REF_CLK2_P/N = 156.25MHz
Part number: LS1027AXE7NQA
Serdes protocl selector:
83BB -> SGMII 1T | 10G-QXGMII | PCIe2 x1 | PCIe1 x1

Current RCW is
*
* Frequencies:
* Core -- 1500 MHz
* Platform -- 400 MHz
* DDR -- 1600 MHz
* DDR Data Rate -- 1.600 GT/s
*/

#include <../ls1028asi/ls1028a.rcwi>

SYS_PLL_RAT=4
MEM_PLL_RAT=16
CGA_PLL1_RAT=15
CGA_PLL2_RAT=12
HWA_CGA_M1_CLK_SEL=3
HWA_CGA_M2_CLK_SEL=7
HWA_CGA_M3_CLK_SEL=6
HWA_CGA_M4_CLK_SEL=3
DDR_REFCLK_SEL=2
DRAM_LAT=1
BOOT_LOC=21
FLASH_CFG1=3
SYSCLK_FREQ=600
IIC2_PMUX=6
IIC4_PMUX=2
IIC6_PMUX=3
XSPI1_A_DATA74_PMUX=1
CLK_OUT_PMUX=2
USB3_CLK_FSEL=39
ENETC_RCW=3
SRDS_PRTCL_S1_L0=1
SRDS_PRTCL_S1_L1=3
SRDS_PRTCL_S1_L2=11
SRDS_PRTCL_S1_L3=11
SRDS_PLL_REF_CLK_SEL_S1=0

/* Added DDR tests */
SRDS_PLL_PD_PLL1=0
SRDS_PLL_PD_PLL2=0

/* Errata for PCIe controller */
#include <../ls1028asi/a008851.rcw>
#include <../ls1028asi/a010477.rcw>
#include <../ls1028asi/a009531.rcw>

/* Increase FSPI clock frequency */
#include <../ls1028asi/fspi_speed.rcw>

I managed to get some logs but ignoring RESET_REQ on my system controller

[ 1.500433] lynx-10g 1ea0000.phy: PLLF: enabled, unlocked, reference clock 100MHz, clock net 5GHz
[ 1.509408] lynx-10g 1ea0000.phy: Supported interfaces and link modes:
[ 1.516086] lynx-10g 1ea0000.phy: sgmii
[ 1.520132] lynx-10g 1ea0000.phy: 1000base-x
[ 1.524616] lynx-10g 1ea0000.phy: 1000baseKX/Full
[ 1.529539] lynx-10g 1ea0000.phy: qsgmii
[ 1.533671] lynx-10g 1ea0000.phy: PLLS: enabled, unlocked, reference clock 156.25MHz, clock net 5.15625GHz
[ 1.543420] lynx-10g 1ea0000.phy: Supported interfaces and link modes:
[ 1.550101] lynx-10g 1ea0000.phy: 10g-qxgmii
[ 1.554585] lynx-10g 1ea0000.phy: usxgmii

Re: Serdes PLL RST_ERR on LS1028A

LFGP — Fri, 12 Sep 2025 14:32:02 GMT

yes, we are talking about the same.
The PLL behavior you are facing is documented in the Chip-Errata.
The workarounds I shared, they are well documented, if you want to know the entire context, please open a new case (not community case) so we can provide the documentation.