https://community.nxp.com/t5/Layerscape/LS1046A-RCW-SRC-getting-cleared-in-u-boot/m-p/2115322#M15834 <P>Hi,</P><P>I simply want to check that I can query the PORSR1 register in u-boot and have the value correspond to QSPI.</P><P>My issue is that I have enabled the debug print in u-boot in cpu.c which shows the correct value (meaning cfg_rcw_src[8:0] have been sampled correctly)&nbsp;however when I run "md 0x1ee0000" the top 9 bits of PORSR1 (RCW_SRC) have been cleared. I can't see anywhere in the code where PORSR1 is edited.</P><P>Any ideas on why this may be?</P><P>Thanks,</P><P>Neil</P> Thu, 12 Jun 2025 10:12:03 GMT nl10001 2025-06-12T10:12:03Z https://community.nxp.com/t5/Layerscape/LS1046A-RCW-SRC-getting-cleared-in-u-boot/m-p/2115322#M15834 <P>Hi,</P><P>I simply want to check that I can query the PORSR1 register in u-boot and have the value correspond to QSPI.</P><P>My issue is that I have enabled the debug print in u-boot in cpu.c which shows the correct value (meaning cfg_rcw_src[8:0] have been sampled correctly)&nbsp;however when I run "md 0x1ee0000" the top 9 bits of PORSR1 (RCW_SRC) have been cleared. I can't see anywhere in the code where PORSR1 is edited.</P><P>Any ideas on why this may be?</P><P>Thanks,</P><P>Neil</P> Thu, 12 Jun 2025 10:12:03 GMT https://community.nxp.com/t5/Layerscape/LS1046A-RCW-SRC-getting-cleared-in-u-boot/m-p/2115322#M15834 nl10001 2025-06-12T10:12:03Z https://community.nxp.com/t5/Layerscape/LS1046A-RCW-SRC-getting-cleared-in-u-boot/m-p/2116025#M15837 <P style="margin: 0in; font-family: Calibri; font-size: 11.0pt;"><SPAN>That </SPAN><SPAN>is expected. It happens due to A-010539 workaround implementation.</SPAN></P> <P style="margin: 0in; font-family: Calibri; font-size: 11.0pt;" lang="en-US">Thanks</P> Fri, 13 Jun 2025 09:27:31 GMT https://community.nxp.com/t5/Layerscape/LS1046A-RCW-SRC-getting-cleared-in-u-boot/m-p/2116025#M15837 June_Lu 2025-06-13T09:27:31Z