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    <title>topic Re: Ls1046a internal MDIO registers in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/Ls1046a-internal-MDIO-registers/m-p/2098441#M15753</link>
    <description>Dear &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/195876"&gt;@gkrishna&lt;/a&gt;,&lt;BR /&gt;if you read accesses to reserved addresses you will get 0x0000 as returns.&lt;BR /&gt;&lt;BR /&gt;please review the Chapter 31 SerDes Module LS1046A Reference&lt;BR /&gt;also please review, in the LS1046ADPAARM, the chapter "1.9.3 Frame Manager (FMan) Implementation"&lt;BR /&gt; also please review the chapter 31.7.5 MDIO_KX_PCS register descriptions into the LS1046aRM pdf</description>
    <pubDate>Thu, 15 May 2025 22:15:16 GMT</pubDate>
    <dc:creator>LFGP</dc:creator>
    <dc:date>2025-05-15T22:15:16Z</dc:date>
    <item>
      <title>Ls1046a internal MDIO registers</title>
      <link>https://community.nxp.com/t5/Layerscape/Ls1046a-internal-MDIO-registers/m-p/2096660#M15736</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Could some one tell me the internal mdio registers for PCS access in ls1046a, I am trying to communicate with Mac to mac connection, i am trying to use 1000base kx with backplane driver but the driver has match phy id before probing and that's is failing, because of invalid device IDS which required for c45 clause, but the values should be updated during mdio registers with phy, but doesn't seem that happened, I have enabled everything properly in dts and brought the driver, my only doubt is I think the mdio internal address could be wrong, may be I am using external mdio, but I am not able to differentiate the address through any memory map in reference document. Please some one share the mdio internal and external address range, I am using fmac9 so if anything particular to that fmac then please do share.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Gopi Krishna M&lt;/P&gt;</description>
      <pubDate>Tue, 13 May 2025 16:13:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Ls1046a-internal-MDIO-registers/m-p/2096660#M15736</guid>
      <dc:creator>gkrishna</dc:creator>
      <dc:date>2025-05-13T16:13:09Z</dc:date>
    </item>
    <item>
      <title>Re: Ls1046a internal MDIO registers</title>
      <link>https://community.nxp.com/t5/Layerscape/Ls1046a-internal-MDIO-registers/m-p/2098441#M15753</link>
      <description>Dear &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/195876"&gt;@gkrishna&lt;/a&gt;,&lt;BR /&gt;if you read accesses to reserved addresses you will get 0x0000 as returns.&lt;BR /&gt;&lt;BR /&gt;please review the Chapter 31 SerDes Module LS1046A Reference&lt;BR /&gt;also please review, in the LS1046ADPAARM, the chapter "1.9.3 Frame Manager (FMan) Implementation"&lt;BR /&gt; also please review the chapter 31.7.5 MDIO_KX_PCS register descriptions into the LS1046aRM pdf</description>
      <pubDate>Thu, 15 May 2025 22:15:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Ls1046a-internal-MDIO-registers/m-p/2098441#M15753</guid>
      <dc:creator>LFGP</dc:creator>
      <dc:date>2025-05-15T22:15:16Z</dc:date>
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