topic Re: FlexSPI octal mode in Layerscape

FlexSPI octal mode

fcenedese — Mon, 10 Mar 2025 16:12:54 GMT

Hello

We're using a LX2160A with its integrated FlexSPI controller to access an Everspin MRAM device. Reading and writing with standard commands (0x03/0x02) on a single lane works fine. Now I try to speed it up by using 8 lanes. I did manage to read data but the first byte seems to be duplicated.

This is the table I use in the LUT (I tried both sdr and dtr). The MRAM is configured for 8 dummy cycles, the speed is very low (20MHz):

// read octal sdr
(LUT_CMD, LUT_PAD(1), 0xCB)
(LUT_ADDR, LUT_PAD(8), 24)
(LUT_DUMMY, LUT_PAD(8), LUT_MODE8)
(LUT_NXP_READ, LUT_PAD(8),

->0x0B1804CB, 0x27083307, 0x00000000, 0x00000000

// read octal ddr
(LUT_CMD, LUT_PAD(1), 0xFD)
(LUT_ADDR_DDR, LUT_PAD(8), 32)
(LUT_DUMMY_DDR, LUT_PAD(8), LUT_MODE8)
(LUT_READ_DDR, LUT_PAD(8),

-> 0x8B2004FD, 0xA708B307, 0x00000000, 0x00000000

What could be the reason that I get an additional byte in the beginning with both commands?

Thanks

Re: FlexSPI octal mode

LFGP — Tue, 11 Mar 2025 16:35:24 GMT

dear @fcenedese,

you need to ask to the MRAM vendor in order to check if the commands in the LUT are in the correct order when you want to use 8 lanes, because the problem is in the MRAM side.

Re: FlexSPI octal mode

fcenedese — Thu, 20 Mar 2025 08:05:08 GMT

I have a follow-up question: Reading and writing octal now works. However the speedup in writing was rather small. Checking with an oscilloscope on the SPI bus we saw that each 8-byte write is a separate transaction with write-enable, write command, address and data, then the chip select is reset again.

In the LUT I do have two commands being executed for an AHB write, WE and Write octal. But even if I take out the WE, issue this manually before writing and then write all the values in a loop the chip select still gets deasserted after each data packet. Is it possible to have a burst write with AHB or do I need to do this with an IP command? What is the recommended way to get the most speed out of it?

Interestingly reading octal seems to work fine, all data is read in a continuous burst, even though I'm reading exactly the same way as I'm writing (for loop, pointer dereference).

Thanks

Re: FlexSPI octal mode

LFGP — Tue, 25 Mar 2025 17:42:50 GMT

dear Fabian,
this issue is a little out of our support.
But, writing operations usually require write-enable and may be limited to page sizes or minimum transaction units, at this sense you could develop as next:
>> use the IP commands
>> Keep CS asserted over multiple writes
>> use ""SEQUENCE"" and ""SEQID"" to create bigger transactions.

Note: This is only a suggestion.

Re: FlexSPI octal mode

fcenedese — Wed, 26 Mar 2025 08:00:13 GMT

I would have thought that NXP is the right place to support the FlexSPI controller used in NXP CPUs. Is there another place I can go to ask for help?

How can I keep CS asserted as this is fully controlled by FlexSPI?

Thanks