<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LayerscapeのトピックRe: LS1046A: How to power down a core</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/2036991#M15341</link>
    <description>&lt;P&gt;Happy to help.&amp;nbsp; Good luck!&lt;/P&gt;</description>
    <pubDate>Mon, 03 Feb 2025 02:07:36 GMT</pubDate>
    <dc:creator>Daves_Garage</dc:creator>
    <dc:date>2025-02-03T02:07:36Z</dc:date>
    <item>
      <title>LS1046A: How to power down a core</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/1642353#M12362</link>
      <description>&lt;P&gt;Per my system requirements I need to power down 3 of the 4 cores. Can someone point me to the documentation which discusses how to shut down the specific clocks for 3 of the 4 cores?&lt;/P&gt;&lt;P&gt;Thank you&lt;/P&gt;</description>
      <pubDate>Fri, 28 Apr 2023 15:27:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/1642353#M12362</guid>
      <dc:creator>scottwelsh</dc:creator>
      <dc:date>2023-04-28T15:27:03Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A: How to power down a core</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/1733854#M13433</link>
      <description>&lt;P&gt;Hi Scott,&amp;nbsp; I just was looking into doing this myself when I ran across this unanswered question... I've sort of given up on this forum, as no one seems to respond for a really long time... looks like you asked your question over 5 months ago with no response.&lt;/P&gt;&lt;P&gt;Well, to show you what I did, here's a shot of my notes:&lt;/P&gt;&lt;H1&gt;DISABLING CORES ON LS1046A&lt;/H1&gt;&lt;P class=""&gt;ref: 12.3.11 Core Disable Register (COREDISR)&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;COREDISR&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;provides a mechanism for gating clocks to any cores on the device that are not used when running an application.&lt;/LI&gt;&lt;LI&gt;COREDISR&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;register should only be configured in the following conditions:&lt;UL&gt;&lt;LI&gt;Before system ready, COREDISR register can be programmed by the external debugger or Pre-Boot Initialization.&lt;/LI&gt;&lt;LI&gt;After system ready, a COREDISR register bit can be programmed for the corresponding core by the external debugger or embedded software while the core is in boot-holdoff mode.&lt;/LI&gt;&lt;/UL&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;H2&gt;HOW TO…&lt;/H2&gt;&lt;UL&gt;&lt;LI&gt;DCFG_CCSR&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;base address:&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;0x01EE0000&lt;/LI&gt;&lt;LI&gt;COREDISR&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;address:&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;0x01EE0094&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Value Definition&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;0x000000002&lt;/TD&gt;&lt;TD&gt;Core 1 disabled&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;0x000000004&lt;/TD&gt;&lt;TD&gt;Core 2 disabled&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;0x000000008&lt;/TD&gt;&lt;TD&gt;Core 3 disabled&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P class=""&gt;Values can be OR’d together to disable multiple cores.&lt;/P&gt;&lt;P class=""&gt;Core 0 is always enabled…&lt;/P&gt;&lt;P class=""&gt;Example:&lt;/P&gt;&lt;DIV class=""&gt;&lt;PRE&gt;    &lt;SPAN class=""&gt;//&lt;/SPAN&gt;-------------------------------------------------------------------------
    &lt;SPAN class=""&gt;//&lt;/SPAN&gt; disable core &lt;SPAN class=""&gt;3&lt;/SPAN&gt; and &lt;SPAN class=""&gt;2&lt;/SPAN&gt; so we only use core &lt;SPAN class=""&gt;0&lt;/SPAN&gt; and &lt;SPAN class=""&gt;1&lt;/SPAN&gt;...
    &lt;SPAN class=""&gt;//&lt;/SPAN&gt;-------------------------------------------------------------------------
    write &lt;SPAN class=""&gt;0&lt;/SPAN&gt;xEE0094, &lt;SPAN class=""&gt;0&lt;/SPAN&gt;x0000000C&lt;/PRE&gt;&lt;/DIV&gt;&lt;H1&gt;MODIFY U-BOOT TO REFLECT IDLE CORES&lt;/H1&gt;&lt;UL&gt;&lt;LI&gt;Change code in&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;./u-boot/arch/arm/cpu/armv8/fsl-layerscape/cpu.c&lt;/LI&gt;&lt;/UL&gt;&lt;DIV class=""&gt;&lt;PRE&gt;for_each_cpu(i, core, &lt;SPAN class=""&gt;cpu_numcores&lt;/SPAN&gt;(), &lt;SPAN class=""&gt;cpu_mask&lt;/SPAN&gt;()) {
    &lt;SPAN class=""&gt;if&lt;/SPAN&gt;(!(i % &lt;SPAN class=""&gt;2&lt;/SPAN&gt;)) 
        &lt;SPAN class=""&gt;printf&lt;/SPAN&gt;(&lt;SPAN class=""&gt;"\n\t"&lt;/SPAN&gt;);

    type = &lt;SPAN class=""&gt;TP_ITYP_VER&lt;/SPAN&gt;(&lt;SPAN class=""&gt;fsl_qoriq_core_to_type&lt;/SPAN&gt;(core));

    &lt;SPAN class=""&gt;printf&lt;/SPAN&gt;(&lt;SPAN class=""&gt;"CPU%d(%s):%-4s MHz %s "&lt;/SPAN&gt;, core,
           (type == TY_ITYP_VER_A7) ? &lt;SPAN class=""&gt;"A7 "&lt;/SPAN&gt; :
              (type == TY_ITYP_VER_A53 ? &lt;SPAN class=""&gt;"A53"&lt;/SPAN&gt; :
              (type == TY_ITYP_VER_A57 ? &lt;SPAN class=""&gt;"A57"&lt;/SPAN&gt; :
              (type == TY_ITYP_VER_A72 ? &lt;SPAN class=""&gt;"A72"&lt;/SPAN&gt; : &lt;SPAN class=""&gt;"   "&lt;/SPAN&gt;))),
              &lt;SPAN class=""&gt;strmhz&lt;/SPAN&gt;(buf, sysinfo.freq_processor[core]),
              (&lt;SPAN class=""&gt;in_be32&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0x01EE0094&lt;/SPAN&gt;) &amp;amp; (&lt;SPAN class=""&gt;1&lt;/SPAN&gt;&amp;lt;&amp;lt;core)) ? &lt;SPAN class=""&gt;"[ IDLE ]"&lt;/SPAN&gt; : &lt;SPAN class=""&gt;"[ACTIVE]"&lt;/SPAN&gt;);
    }&lt;/PRE&gt;&lt;/DIV&gt;</description>
      <pubDate>Wed, 04 Oct 2023 16:53:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/1733854#M13433</guid>
      <dc:creator>Daves_Garage</dc:creator>
      <dc:date>2023-10-04T16:53:30Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A: How to power down a core</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/2036987#M15338</link>
      <description>&lt;P&gt;Hi Daves,&lt;/P&gt;&lt;P&gt;I also need to disable cores in my custom LS1046a board.&lt;/P&gt;&lt;P&gt;I added bellow lines in components/firmware/rcw/ls1046a_custom/NN_FNSNPPPP_1133_8888/rcw_1600_qspiboot.rcw:&lt;/P&gt;&lt;P&gt;---&lt;/P&gt;&lt;P&gt;//-------------------------------------------------------------------------&lt;BR /&gt;// disable core 3 and 2 so we only use core 0 and 1...&lt;BR /&gt;.pbi&lt;BR /&gt;write 0x01EE0094, 0x0000000c&lt;BR /&gt;//write 0x01ee0094, 0x0000000e&lt;BR /&gt;.end&lt;/P&gt;&lt;P&gt;---&lt;/P&gt;&lt;P&gt;I rebuilt firmware_ls1046a_custom_qspiboot.img &amp;amp; flashed on my custom board.&lt;BR /&gt;But, nothing displayed in the console.&lt;/P&gt;&lt;P&gt;Is there anything to change more?&lt;/P&gt;&lt;P&gt;Regards,&lt;BR /&gt;Jake&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 03 Feb 2025 01:13:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/2036987#M15338</guid>
      <dc:creator>changjake</dc:creator>
      <dc:date>2025-02-03T01:13:45Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A: How to power down a core</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/2036989#M15339</link>
      <description>&lt;P&gt;Hi Jake,&lt;/P&gt;&lt;P&gt;My guess there's no response on the serial output is because you threw an error during the PBL portion of the boot process... The LS1046A is not very friendly if the RCW or the PBL is wrong; if the CRC doesn't match, it simply stops and sets the RESET_REQ line to reboot itself... which sends it into an endless loop if that's how your hardware is setup... &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/P&gt;&lt;P&gt;The problem with your code is the address.&amp;nbsp; The commands in the PBL strip off the most significant (1) in your address, and incorporate it into the WRITE macro you're using.&lt;/P&gt;&lt;P&gt;If you change your PBL line to this:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;.pbi&lt;BR /&gt;write 0x0EE0094, 0x0000000c&lt;BR /&gt;.end&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;it probably will work for you...&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hope this helps.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-Dave&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 03 Feb 2025 01:29:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/2036989#M15339</guid>
      <dc:creator>Daves_Garage</dc:creator>
      <dc:date>2025-02-03T01:29:21Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A: How to power down a core</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/2036990#M15340</link>
      <description>Hi Dave,&lt;BR /&gt;It works!&lt;BR /&gt;Thank you so much.&lt;BR /&gt;&lt;BR /&gt;Regards,&lt;BR /&gt;Jake</description>
      <pubDate>Mon, 03 Feb 2025 01:54:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/2036990#M15340</guid>
      <dc:creator>changjake</dc:creator>
      <dc:date>2025-02-03T01:54:33Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A: How to power down a core</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/2036991#M15341</link>
      <description>&lt;P&gt;Happy to help.&amp;nbsp; Good luck!&lt;/P&gt;</description>
      <pubDate>Mon, 03 Feb 2025 02:07:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046A-How-to-power-down-a-core/m-p/2036991#M15341</guid>
      <dc:creator>Daves_Garage</dc:creator>
      <dc:date>2025-02-03T02:07:36Z</dc:date>
    </item>
  </channel>
</rss>

