<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: LS1046 bringup stuck in BL2, DDR init failed in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1046-bringup-stuck-in-BL2-DDR-init-failed/m-p/2030483#M15288</link>
    <description>&lt;P&gt;Yes,&amp;nbsp;&lt;SPAN&gt;CodeWarrior gets the DQ Mapping from the running board.&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Mon, 20 Jan 2025 08:52:09 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2025-01-20T08:52:09Z</dc:date>
    <item>
      <title>LS1046 bringup stuck in BL2, DDR init failed</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046-bringup-stuck-in-BL2-DDR-init-failed/m-p/2029115#M15278</link>
      <description>&lt;P&gt;We have a custom LS1046 board with DDR4. I have mapped DQ lines and got a successful CodeWarrior DDR validation and passed Operational DDR tests with ECC disabled, and speed 1300 MT/s. I have 4 x 1Gb x 16 DDR4 devices fitted.&lt;/P&gt;&lt;P&gt;I've taken the ddr_init1.c output and applied it to my atf version lf-5.10.52-2.1.0.&lt;/P&gt;&lt;P&gt;BL2 fails to boot from SD Card (DDR init failed). If I use the ddr_raw_timing structure from Codewarrior (no&amp;nbsp;CONFIG_STATIC_DDR) I get:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;INFO: SoC workaround for Errata A008850 Early-Phase was applied&lt;BR /&gt;INFO: SoC workaround for Errata A010539 was applied&lt;BR /&gt;INFO: RCW BOOT SRC is SD/EMMC&lt;BR /&gt;INFO: SoC workaround for DDR Errata A008511 was applied&lt;BR /&gt;INFO: SoC workaround for DDR Errata A009803 was applied&lt;BR /&gt;INFO: SoC workaround for DDR Errata A009942 was applied&lt;BR /&gt;INFO: SoC workaround for DDR Errata A010165 was applied&lt;BR /&gt;INFO: time base 0 ms&lt;BR /&gt;NOTICE: Fixed DDR on board&lt;BR /&gt;INFO: Time after parsing SPD 4 ms&lt;BR /&gt;ERROR: Board parameters no match.&lt;BR /&gt;ERROR: Failed matching board timing.&lt;BR /&gt;ERROR: DDR Clk: MCLK cycle is 481 ps.&lt;BR /&gt;ERROR: DDR Clk is faster than DIMM can support.&lt;BR /&gt;ERROR: mclk 481 invalid&lt;BR /&gt;ERROR: cas latency is too large 42&lt;BR /&gt;ERROR: Calculating DDR registers failed&lt;BR /&gt;ERROR: Calculate register error&lt;BR /&gt;ERROR: DDR init failed.&lt;BR /&gt;INFO: SoC workaround for Errata A008850 Post-Phase was applied&lt;BR /&gt;INFO: RCW BOOT SRC is SD/EMMC&lt;BR /&gt;INFO: esdhc_emmc_init&lt;BR /&gt;INFO: Card detected successfully&lt;BR /&gt;INFO: init done:&lt;BR /&gt;NOTICE: Incorrect DRAM0 size is defined in platform_def.h&lt;BR /&gt;ERROR: mmap_add_region_check() failed. error -22&lt;BR /&gt;ERROR: mmap_add_region_check() failed. error -22&lt;BR /&gt;NOTICE: BL2: v2.4(release):lf-5.10.52-2.1.0-rc2-0-gbb4957067-dirty&lt;BR /&gt;NOTICE: BL2: Built : 14:21:46, Jan 16 2025&lt;BR /&gt;INFO: Configuring TrustZone Controller&lt;BR /&gt;INFO: BL2: Doing platform setup&lt;BR /&gt;INFO: BL2: Loading image id 3&lt;BR /&gt;INFO: sd-mmc read done.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;If I define&amp;nbsp;CONFIG_STATIC_DDR and use the static_1300 struct from Codewarrior I get:&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;INFO: SoC workaround for Errata A008850 Early-Phase was applied&lt;BR /&gt;INFO: SoC workaround for Errata A010539 was applied&lt;BR /&gt;INFO: RCW BOOT SRC is SD/EMMC&lt;BR /&gt;INFO: SoC workaround for DDR Errata A008511 was applied&lt;BR /&gt;INFO: SoC workaround for DDR Errata A009803 was applied&lt;BR /&gt;INFO: SoC workaround for DDR Errata A009942 was applied&lt;BR /&gt;INFO: SoC workaround for DDR Errata A010165 was applied&lt;BR /&gt;INFO: Time before programming controller 0 ms&lt;BR /&gt;WARNING: Warning: Optimal CPO value not set.&lt;BR /&gt;ERROR: Found training error(s): 0x3000&lt;BR /&gt;ERROR: Error: Waiting for D_INIT timeout.&lt;BR /&gt;ERROR: Writing DDR register(s) failed&lt;BR /&gt;ERROR: Programing DDRC error&lt;BR /&gt;ERROR: DDR init failed.&lt;BR /&gt;INFO: SoC workaround for Errata A008850 Post-Phase was applied&lt;BR /&gt;INFO: RCW BOOT SRC is SD/EMMC&lt;BR /&gt;INFO: esdhc_emmc_init&lt;BR /&gt;INFO: Card detected successfully&lt;BR /&gt;INFO: init done:&lt;BR /&gt;NOTICE: Incorrect DRAM0 size is defined in platform_def.h&lt;BR /&gt;ERROR: mmap_add_region_check() failed. error -22&lt;BR /&gt;ERROR: mmap_add_region_check() failed. error -22&lt;BR /&gt;NOTICE: BL2: v2.4(release):lf-5.10.52-2.1.0-rc2-0-gbb4957067-dirty&lt;BR /&gt;NOTICE: BL2: Built : 14:52:12, Jan 16 2025&lt;BR /&gt;INFO: Configuring TrustZone Controller&lt;BR /&gt;INFO: BL2: Doing platform setup&lt;BR /&gt;INFO: BL2: Loading image id 3&lt;BR /&gt;INFO: sd-mmc read done.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I can see DDR clock on a scope at 650MHz. I'm fairly confident on the DQ map as I've double checked, and DDR Validation passed.&lt;/P&gt;&lt;P&gt;Does anyone have any ideas what I should do next?&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;/BLOCKQUOTE&gt;</description>
      <pubDate>Thu, 16 Jan 2025 15:01:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046-bringup-stuck-in-BL2-DDR-init-failed/m-p/2029115#M15278</guid>
      <dc:creator>SimonRo</dc:creator>
      <dc:date>2025-01-16T15:01:43Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046 bringup stuck in BL2, DDR init failed</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046-bringup-stuck-in-BL2-DDR-init-failed/m-p/2029558#M15282</link>
      <description>&lt;P&gt;Please boot ATF on the target board, then connect CodeWarrior to the target board to create a QCVS DDR project with "From target" method, then check whether the generated DDR controller configuration parameters are same with what you provided in ATF source code.&lt;/P&gt;</description>
      <pubDate>Fri, 17 Jan 2025 06:58:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046-bringup-stuck-in-BL2-DDR-init-failed/m-p/2029558#M15282</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2025-01-17T06:58:06Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046 bringup stuck in BL2, DDR init failed</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046-bringup-stuck-in-BL2-DDR-init-failed/m-p/2029774#M15284</link>
      <description>&lt;P&gt;When I do this should all properties match, e.g. does CodeWarrior get the DQ Mapping from the running board?&amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm seeing a lot of difference in the DQ mapping for example.&lt;/P&gt;</description>
      <pubDate>Fri, 17 Jan 2025 13:08:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046-bringup-stuck-in-BL2-DDR-init-failed/m-p/2029774#M15284</guid>
      <dc:creator>SimonRo</dc:creator>
      <dc:date>2025-01-17T13:08:15Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046 bringup stuck in BL2, DDR init failed</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1046-bringup-stuck-in-BL2-DDR-init-failed/m-p/2030483#M15288</link>
      <description>&lt;P&gt;Yes,&amp;nbsp;&lt;SPAN&gt;CodeWarrior gets the DQ Mapping from the running board.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 20 Jan 2025 08:52:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1046-bringup-stuck-in-BL2-DDR-init-failed/m-p/2030483#M15288</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2025-01-20T08:52:09Z</dc:date>
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  </channel>
</rss>

