LS1046A DPPA IF_STATUS Register

DaT63 — Thu, 02 Jan 2025 16:44:37 GMT

Hi,

I need to programmatically read register IF_STATUS (offset 0x304) of the Frame Manager EMAC3 that should be at address 0x1AE4304. Of this register only the nibble 16-19 is meaningful because the other bits are reserved. The value of the nibble that I read is 0xD (or 0b1101) that seems correct because the bits indicate:

- a valid link is established by the RGMII PHY

- 1 Gbps

- RGMII full duplex link is established

What it looks weird to me is that the full 32-bit value I read is:

0x00D00000

i.e. the 0xD nibble does not appear to be in the right position because it occupies bits 20-23. Changing the endianity by byte swapping does not help because in this case the value would be

0x0000D000

and the nibble would occupy bits 12-15

What am I doing wrong here?

Thanks in advance for the support

Re: LS1046A DPPA IF_STATUS Register

yipingwang — Mon, 13 Jan 2025 08:47:37 GMT

The DPAA components should be in big-endian mode. The DPAA software should perform endianness-related byte-swap.

The 0xD nibble occupies bits 16-19.

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LS1046A DPPA IF_STATUS Register

Re: LS1046A DPPA IF_STATUS Register