ls1021 DDR ECC MSE

floac — Thu, 02 Jan 2025 02:03:56 GMT

请问在ls1021a中。DDR ECC的 MSE（内存选择错误），是如何触发的该错误中断的（触发条件是什么）？MSE中断捕捉到的异常地址（capture_address）有用吗？谢谢。

Re: ls1021 DDR ECC MSE

SebastianG — Fri, 03 Jan 2025 23:34:19 GMT

HI @floac,

Just to let you know that I am working on your question, When I have any update I will let you know

Regards

Re: ls1021 DDR ECC MSE

Hector_Villarruel — Fri, 24 Jan 2025 20:15:27 GMT

Hello @floac

Hope this email finds you well,

Please refer to the section 16.4.72 Memory error detect (ERR_DETECT). from QorIQ LS1021A Reference Manual, Rev. 3.1, 02/2020.

"The memory error detect register stores the detection bits for multiple memory errors,
single- and multiple-bit ECC errors, and memory select errors. It is a read/write register.
A bit can be cleared by writing a one to the bit. System software can determine the type
of memory error by examining the contents of this register. If an error is disabled with
ERR_DISABLE, the corresponding error is never detected or captured in
ERR_DETECT."

In addition, please refer to the 16.5.8 Error Management from the
QorIQ LS1021A Reference Manual, Rev. 3.1, 02/2020

"The DDR memory controller detects four different kinds of errors: training, single-bit,
multi-bit, and memory select errors. The following discussion assumes all the relevant
error detection, correction, and reporting functions are enabled as described in Memory
error interrupt enable (ERR_INT_EN), Memory error disable (ERR_DISABLE), and
Memory error detect (ERR_DETECT)
Single-bit errors are counted and reported based on the ERR_SBE value. When a singlebit error is detected, the DDR memory controller does the following:
• Corrects the data
• Increments the single-bit error counter ERR_SBE[SBEC]
• Generates a critical interrupt if the counter value ERR_SBE[SBEC] equals the
programmable threshold ERR_SBE[SBET]
• Completes the transaction normally "

Have a great day.

Hector Villarruel S

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