LayerscapeのトピックRe: LS1046A L1 and L2 cache ECC

LS1046A L1 and L2 cache ECC

DaT63 — Fri, 29 Nov 2024 15:08:13 GMT

Is ECC enabled by default for L1 and L2 caches on the LS1046A?

I know that this information is contained in register L2CTLR_EL1 , but I wonder if it is possible by program to access this register

Thanks in advance

Re: LS1046A L1 and L2 cache ECC

Hector_Villarruel — Thu, 05 Dec 2024 02:33:53 GMT

Hello @DaT63

Hope this email finds you well,

I apologize for the short delay regarding this case.

I would like to inform you that So for L1 instruction, L1 data, and L2 caches, a Single-bit ECC correction is always enabled and is handled siliently.

Regarding the L2CTLR_EL1, in order to avoid any kind of confusion and keep the information as clear as possible, could you please let us know the register location in our LS1046A documentation?

Have a great day.

Best Regards,

Hector Villarruel

Re: LS1046A L1 and L2 cache ECC

DaT63 — Thu, 05 Dec 2024 10:36:53 GMT

Hi @Hector_Villarruel ,

thank you for the reply. The L2CTLR_EL1 register is indicated in the ARM® Cortex®-A72 MPCore Processor TRM that is accompanying the LS1046A Reference Manual. In any case if you state that ECC is always enabled I do not need to check such a register and I can accept your reply as solution

KInd Regards

Re: LS1046A L1 and L2 cache ECC

Hector_Villarruel — Fri, 06 Dec 2024 21:05:56 GMT

Hello @DaT63

Hope this post finds you well,

Yes, that is right.

As I inform you on my last reply:

L1 instruction, L1 data, and L2 caches, a Single-bit ECC correction is always enabled and is handled siliently.

Have a great day.

BR,

Hector V