Inquiry Regarding SDHC1 and SDHC2 Configuration in LS1012A

Dhanyalakshmi — Tue, 22 Oct 2024 06:13:40 GMT

Dear Support Team,

I hope this message finds you well.

I am currently working with the FRWY-LS1012A evaluation board and have a question regarding the configuration of the Secure Digital Host Controllers (SDHC1 and SDHC2) in the Reset Configuration Word (RCW).

While I understand that SDHC1 is the primary controller dedicated to the SD card slot, I have noticed that there are no references to SDHC1_DAT0, SDHC1_DAT1, SDHC1_DAT2, SDHC1_DAT3, SDHC1_CLK, or SDHC1_CMD in the RCW file. In contrast, SDHC2_DAT0 and other associated signals are explicitly mentioned.

The RCW file is located at:
~/distro/build-ls1012afrwy/tmp/work/ls1012afrwy-fsl-linux/rcw/git-r0/git/ls1012afrwy
I obtained this file after building the recipe using the Yocto Project.

Here is the content of the file for your reference:

%size=512
%sysaddr=ee0100
%pbladdr=610000

SYS_PLL_CFG[0:1]
SYS_PLL_RAT[2:6]
CGA_PLL1_CFG[24:25]
CGA_PLL1_RAT[26:31]
C1_PLL_SEL[96:99]
SRDS_PRTCL_S1[128:143]
FM1_MAC_RAT[158]
SRDS_PLL1_REF_CLK_SEL_S1[160]
SRDS_PLL2_REF_CLK_SEL_S1[161]
USB_REFCLK_SEL[164]
RGMII_REFCLK_SEL[165]
RGMII_CLK_DCC[166]
HDLC2_MODE[167]
SRDS_PLL_PD_S1[168:169]
SRDS_DIV_PEX[176:177]
SRDS_REFCLK_SEL[188]
SRDS_INT_REFCLK[189]
PBI_SRC[192:195]
BOOT_HO[201]
SB_EN[202]
DDR_RATE[232]
DDR_RSV0[234]
SYS_PLL_SPD[242:243]
CGA_PLL1_SPD[244]
HOST_AGT_PEX[264]
GP_INFO[288:319]
SDHC2_EXT_CLK[354]
SDHC2_EXT_CMD[355]
SDHC2_EXT_DAT3[356]
SDHC2_EXT_DAT2[357]
SDHC2_EXT_DAT1[358]
SDHC2_EXT_DAT0[359]
EC1_EXT_SAI3[360:361]
EC1_EXT_SAI4[362:363]
EC1_EXT_SAI2_TX[364]
EC1_EXT_SAI2_RX[365]
EC1_BASE[366:367]
UART1_BASE[368:369]
UART2_BASE_FLOW[370:371]
SDHC1_BASE[372:373]
SDHC2_BASE_DAT321[374:375]
SDHC2_BASE_BASE[376:377]
UART2_BASE_DATA[378]
EMI1_BASE[379]
GPIO_FTM_EXTCLK_BASE[380:381]
CLK_OUT_BASE[382:383]
SDHC1_CD[419]
SDHC1_WP[420]
QSPI_DATA0_GPIO[421]
QSPI_DATA1_GPIO[422:423]
QSPI_IIC2[424:425]
USB1_DRVVBUS_BASE[429:430]
USB1_PWRFAULT_BASE[431:432]
SDHC1_VSEL[434]
EMI1_DMODE[438]
EVDD_VSEL[439:440]
IIC1_BASE[441:442]
EMI1_CMODE[444]
SYSCLK_FREQ[472:481]

Given that the RCW mentions the functionality of pins, could you please clarify why there are no references to the SDHC1 data and command lines?

I appreciate your assistance and hope to receive a prompt response.

Thank you.

Re: Inquiry Regarding SDHC1 and SDHC2 Configuration in LS1012A

June_Lu — Tue, 22 Oct 2024 14:21:34 GMT

Please kindly find the RCW setting related to SDHC1 in LS1012A Reference Manual, page 208, 3.4.3 eSDHC1 and GPIO1 signal multiplexing.

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Inquiry Regarding SDHC1 and SDHC2 Configuration in LS1012A

Re: Inquiry Regarding SDHC1 and SDHC2 Configuration in LS1012A