<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: LX2160ARDB-REV2 boot from Invalid setting ,xmap 7 in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/LX2160ARDB-REV2-boot-from-Invalid-setting-xmap-7/m-p/1953206#M14879</link>
    <description>&lt;P&gt;Please refer to the following source code in&amp;nbsp;board/freescale/lx2160a/lx2160a.c&lt;/P&gt;
&lt;P&gt;sw = QIXIS_READ(arch);&lt;BR /&gt;printf("Board version: %c, boot from ", (sw &amp;amp; 0xf) - 1 + 'A');&lt;/P&gt;
&lt;P&gt;if (src== BOOT_SOURCE_SD_MMC) {&lt;BR /&gt;puts("SD\n");&lt;BR /&gt;} else if (src== BOOT_SOURCE_SD_MMC2) {&lt;BR /&gt;puts("eMMC\n");&lt;BR /&gt;} else {&lt;BR /&gt;sw = QIXIS_READ(brdcfg[0]);&lt;BR /&gt;sw = (sw &amp;gt;&amp;gt; QIXIS_XMAP_SHIFT) &amp;amp; QIXIS_XMAP_MASK;&lt;BR /&gt;switch (sw) {&lt;BR /&gt;case 0:&lt;BR /&gt;case 4:&lt;BR /&gt;puts("FlexSPI DEV#0\n");&lt;BR /&gt;break;&lt;BR /&gt;case 1:&lt;BR /&gt;puts("FlexSPI DEV#1\n");&lt;BR /&gt;break;&lt;BR /&gt;case 2:&lt;BR /&gt;case 3:&lt;BR /&gt;puts("FlexSPI EMU\n");&lt;BR /&gt;break;&lt;BR /&gt;default:&lt;BR /&gt;printf("invalid setting, xmap: %d\n", sw);&lt;BR /&gt;break;&lt;BR /&gt;}&lt;/P&gt;
&lt;P&gt;It means CPLD register&amp;nbsp;BRDCFG0 wasn't read correctly.&lt;/P&gt;
&lt;P&gt;Please refer to section "3.44 Board Configuration 0 (BRDCFG0)" in the attached document.&lt;/P&gt;</description>
    <pubDate>Thu, 12 Sep 2024 07:29:27 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2024-09-12T07:29:27Z</dc:date>
    <item>
      <title>LX2160ARDB-REV2 boot from Invalid setting ,xmap 7</title>
      <link>https://community.nxp.com/t5/Layerscape/LX2160ARDB-REV2-boot-from-Invalid-setting-xmap-7/m-p/1948880#M14856</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;SPAN&gt;Team&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I want to start the Board through xspi, but I see "Board: LX2160AE Rev2.0-RDB, Board version: O, boot from invalid setting, xmap: 7" in the log.&lt;/SPAN&gt;&lt;/P&gt;&lt;PRE&gt;&amp;lt;NPU Ready&amp;gt;&lt;BR /&gt;NOTICE: BL2: v2.4(release):&lt;BR /&gt;NOTICE: BL2: Built : 10:26:27, Sep 3 2024&lt;BR /&gt;NOTICE: UDIMM CBD32D4S2S8MR-8 &lt;BR /&gt;NOTICE: DDR PMU Hardware version-0x1210&lt;BR /&gt;NOTICE: DDR PMU Firmware vision-0x1001 (vA-2019.04)&lt;BR /&gt;NOTICE: DDR4 UDIMM with 1-rank 64-bit bus (x8)&lt;BR /&gt;&lt;BR /&gt;NOTICE: 8 GB DDR4, 64-bit, CL=22, ECC off&lt;BR /&gt;NOTICE: BL2: Booting BL31&lt;BR /&gt;NOTICE: BL31: v2.4(release):&lt;BR /&gt;NOTICE: BL31: Built : 10:26:26, Sep 3 2024&lt;BR /&gt;NOTICE: Welcome to lx2160ardb BL31 Phase&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;U-Boot 2021.04 (Sep 03 2024 - 10:26:20 +0800)&lt;BR /&gt;&lt;BR /&gt;SoC: LX2160AE Rev2.0 (0x87361020)&lt;BR /&gt;Clock Configuration:&lt;BR /&gt;CPU0(A72):2200 MHz CPU1(A72):2200 MHz CPU2(A72):2200 MHz &lt;BR /&gt;CPU3(A72):2200 MHz CPU4(A72):2200 MHz CPU5(A72):2200 MHz &lt;BR /&gt;CPU6(A72):2200 MHz CPU7(A72):2200 MHz CPU8(A72):2200 MHz &lt;BR /&gt;CPU9(A72):2200 MHz CPU10(A72):2200 MHz CPU11(A72):2200 MHz &lt;BR /&gt;CPU12(A72):2200 MHz CPU13(A72):2200 MHz CPU14(A72):2200 MHz &lt;BR /&gt;CPU15(A72):2200 MHz &lt;BR /&gt;Bus: 750 MHz DDR: 3200 MT/s&lt;BR /&gt;Reset Configuration Word (RCW):&lt;BR /&gt;00000000: 5883833c 24580058 00000000 00000000&lt;BR /&gt;00000010: 00000000 0c010000 00000000 00000000&lt;BR /&gt;00000020: 01e001a0 00002580 00000000 1800064e&lt;BR /&gt;00000030: 08250400 00000001 00000000 00000000&lt;BR /&gt;00000040: 00000000 00000000 00000000 00000000&lt;BR /&gt;00000050: 00000000 00000000 00000000 00000000&lt;BR /&gt;00000060: 00000000 00000000 00027088 00000000&lt;BR /&gt;00000070: 00a80031 00150032&lt;BR /&gt;Model: NXP Layerscape LX2160ARDB Board&lt;BR /&gt;Board: LX2160AE Rev2.0-RDB, Board version: O, boot from invalid setting, xmap: 7&lt;BR /&gt;FPGA: v255.255&lt;BR /&gt;SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz&lt;BR /&gt;SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz&lt;BR /&gt;SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz&lt;BR /&gt;VID: Bus 0 has no device with address 0x63&lt;BR /&gt;VID: Couldn't read sensor abort VID adjustment&lt;BR /&gt;core voltage not adjusted&lt;BR /&gt;DRAM: 7.9 GiB&lt;BR /&gt;DDR 7.9 GiB (DDR4, 64-bit, CL=22, ECC off)&lt;BR /&gt;PCA: failed to select proper channel&lt;BR /&gt;Using SERDES1 Protocol: 8 (0x8)&lt;BR /&gt;Using SERDES2 Protocol: 5 (0x5)&lt;BR /&gt;Using SERDES3 Protocol: 0 (0x0)&lt;BR /&gt;SERDES3[PRTCL] = 0x0 is not valid&lt;BR /&gt;PCIe1: pcie@3400000 disabled&lt;BR /&gt;PCIe2: pcie@3500000 disabled&lt;BR /&gt;PCIe3: pcie@3600000 Root Complex: no link&lt;BR /&gt;PCIe4: pcie@3700000 disabled&lt;BR /&gt;PCIe5: pcie@3800000 disabled&lt;BR /&gt;PCIe6: pcie@3900000 disabled&lt;BR /&gt;WDT: Started with servicing (30s timeout)&lt;BR /&gt;MMC: FSL_SDHC: 0, FSL_SDHC: 1&lt;BR /&gt;Loading Environment from SPIFlash... SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB&lt;BR /&gt;*** Warning - bad CRC, using default environment&lt;BR /&gt;&lt;BR /&gt;EEPROM: Invalid ID (ff ff ff ff)&lt;BR /&gt;In: serial_pl01x&lt;BR /&gt;Out: serial_pl01x&lt;BR /&gt;Err: serial_pl01x&lt;BR /&gt;SEC0: RNG instantiated&lt;BR /&gt;Net: &lt;BR /&gt;Warning: DPMAC3@usxgmii (eth0) using random MAC address - 5e:df:5d:a5:7a:98&lt;BR /&gt;&lt;BR /&gt;Warning: DPMAC4@usxgmii (eth1) using random MAC address - a2:e1:07:33:60:c7&lt;BR /&gt;&lt;BR /&gt;Warning: DPMAC5@25g-aui (eth2) using random MAC address - 5a:a6:ad:bc:e1:7e&lt;BR /&gt;&lt;BR /&gt;Warning: DPMAC6@usxgmii (eth3) using random MAC address - fa:e3:56:29:f3:12&lt;BR /&gt;&lt;BR /&gt;Warning: DPMAC17@rgmii-id (eth4) using random MAC address - 92:c0:55:9f:c2:a0&lt;BR /&gt;&lt;BR /&gt;Warning: DPMAC18@rgmii-id (eth5) using random MAC address - ce:ea:c1:c9:d2:3d&lt;BR /&gt;eth0: DPMAC3@usxgmii, eth1: DPMAC4@usxgmii, eth2: DPMAC5@25g-aui, eth3: DPMAC6@usxgmii, eth4: DPMAC17@rgmii-id, eth5: DPMAC18@rgmii-id&lt;BR /&gt;SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB&lt;BR /&gt;device 0 offset 0x640000, size 0x80000&lt;BR /&gt;SF: 524288 bytes @ 0x640000 Read: OK&lt;BR /&gt;device 0 offset 0xa00000, size 0x300000&lt;BR /&gt;SF: 3145728 bytes @ 0xa00000 Read: OK&lt;BR /&gt;device 0 offset 0xe00000, size 0x100000&lt;BR /&gt;SF: 1048576 bytes @ 0xe00000 Read: OK&lt;BR /&gt;crc32+ &lt;BR /&gt;fsl-mc: Booting Management Complex ... SUCCESS&lt;BR /&gt;fsl-mc: Management Complex booted (version: 10.30.0, boot status: 0x1)&lt;BR /&gt;Hit any key to stop autoboot: 0 &lt;BR /&gt;SF: Detected mx25um51245g with page size 256 Bytes, erase size 16 KiB, total 64 MiB&lt;BR /&gt;device 0 offset 0x6c0000, size 0x40000&lt;BR /&gt;SF: 262144 bytes @ 0x6c0000 Read: OK&lt;BR /&gt;device 0 offset 0xd00000, size 0x100000&lt;BR /&gt;SF: 1048576 bytes @ 0xd00000 Read: OK&lt;BR /&gt;starting USB...&lt;BR /&gt;Bus usb3@3100000: Register 200017f NbrPorts 2&lt;BR /&gt;Starting the controller&lt;BR /&gt;USB XHCI 1.00&lt;BR /&gt;Bus usb3@3110000: Register 200017f NbrPorts 2&lt;BR /&gt;Starting the controller&lt;BR /&gt;USB XHCI 1.00&lt;BR /&gt;scanning bus usb3@3100000 for devices... 1 USB Device(s) found&lt;BR /&gt;scanning bus usb3@3110000 for devices... 1 USB Device(s) found&lt;BR /&gt;scanning usb for storage devices... 0 Storage Device(s) found&lt;BR /&gt;&lt;BR /&gt;Device 0: unknown device&lt;BR /&gt;MMC: no card present&lt;BR /&gt;switch to partitions #0, OK&lt;BR /&gt;mmc1(part 0) is current device&lt;BR /&gt;Scanning mmc 1:1...&lt;BR /&gt;Found U-Boot script /lx2160ardb_boot.scr&lt;BR /&gt;1372 bytes read in 5 ms (267.6 KiB/s)&lt;BR /&gt;## Executing script at 80000000&lt;BR /&gt;30659072 bytes read in 110 ms (265.8 MiB/s)&lt;BR /&gt;49935 bytes read in 6 ms (7.9 MiB/s)&lt;BR /&gt;## Flattened Device Tree blob at 90000000&lt;BR /&gt;Booting using the fdt blob at 0x90000000&lt;BR /&gt;Loading Device Tree to 000000009fff0000, end 000000009ffff30e ... OK&lt;BR /&gt;fsl-mc: Deploying data path layout ... WARNING: Firmware returned an error (GSR: 0x3f)&lt;BR /&gt;&lt;BR /&gt;Starting kernel ...&lt;/PRE&gt;&lt;P&gt;&lt;SPAN&gt;How can I solve this problem?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 06 Sep 2024 08:10:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LX2160ARDB-REV2-boot-from-Invalid-setting-xmap-7/m-p/1948880#M14856</guid>
      <dc:creator>Lee_1</dc:creator>
      <dc:date>2024-09-06T08:10:13Z</dc:date>
    </item>
    <item>
      <title>Re: LX2160ARDB-REV2 boot from Invalid setting ,xmap 7</title>
      <link>https://community.nxp.com/t5/Layerscape/LX2160ARDB-REV2-boot-from-Invalid-setting-xmap-7/m-p/1953206#M14879</link>
      <description>&lt;P&gt;Please refer to the following source code in&amp;nbsp;board/freescale/lx2160a/lx2160a.c&lt;/P&gt;
&lt;P&gt;sw = QIXIS_READ(arch);&lt;BR /&gt;printf("Board version: %c, boot from ", (sw &amp;amp; 0xf) - 1 + 'A');&lt;/P&gt;
&lt;P&gt;if (src== BOOT_SOURCE_SD_MMC) {&lt;BR /&gt;puts("SD\n");&lt;BR /&gt;} else if (src== BOOT_SOURCE_SD_MMC2) {&lt;BR /&gt;puts("eMMC\n");&lt;BR /&gt;} else {&lt;BR /&gt;sw = QIXIS_READ(brdcfg[0]);&lt;BR /&gt;sw = (sw &amp;gt;&amp;gt; QIXIS_XMAP_SHIFT) &amp;amp; QIXIS_XMAP_MASK;&lt;BR /&gt;switch (sw) {&lt;BR /&gt;case 0:&lt;BR /&gt;case 4:&lt;BR /&gt;puts("FlexSPI DEV#0\n");&lt;BR /&gt;break;&lt;BR /&gt;case 1:&lt;BR /&gt;puts("FlexSPI DEV#1\n");&lt;BR /&gt;break;&lt;BR /&gt;case 2:&lt;BR /&gt;case 3:&lt;BR /&gt;puts("FlexSPI EMU\n");&lt;BR /&gt;break;&lt;BR /&gt;default:&lt;BR /&gt;printf("invalid setting, xmap: %d\n", sw);&lt;BR /&gt;break;&lt;BR /&gt;}&lt;/P&gt;
&lt;P&gt;It means CPLD register&amp;nbsp;BRDCFG0 wasn't read correctly.&lt;/P&gt;
&lt;P&gt;Please refer to section "3.44 Board Configuration 0 (BRDCFG0)" in the attached document.&lt;/P&gt;</description>
      <pubDate>Thu, 12 Sep 2024 07:29:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LX2160ARDB-REV2-boot-from-Invalid-setting-xmap-7/m-p/1953206#M14879</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2024-09-12T07:29:27Z</dc:date>
    </item>
    <item>
      <title>Re: LX2160ARDB-REV2 boot from Invalid setting ,xmap 7</title>
      <link>https://community.nxp.com/t5/Layerscape/LX2160ARDB-REV2-boot-from-Invalid-setting-xmap-7/m-p/1962215#M14928</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;SPAN&gt;&lt;SPAN class=""&gt;yipingwang&lt;/SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;Thank you for your help.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I don't know why the value read from the register BRDCFG0(050h) is 0xFF.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Do you have any other suggestions to help me solve the problem?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;BR&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 26 Sep 2024 03:25:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LX2160ARDB-REV2-boot-from-Invalid-setting-xmap-7/m-p/1962215#M14928</guid>
      <dc:creator>Lee_1</dc:creator>
      <dc:date>2024-09-26T03:25:25Z</dc:date>
    </item>
  </channel>
</rss>

