How to initialize two DDRC in parallel with UDIMM(no dimm) in LX2160

Zburid — Thu, 22 Aug 2024 07:31:21 GMT

Hi NXP experts,

I am trying to optimize the ATF boot time, and it shows the DDRC initialize will cost too much time; The code annotation of ddrc_set_regs shows that:

/* * If supported by the platform, writing to DDR controller takes two * passes to deassert DDR reset to comply with JEDEC specs for RDIMMs. */ int ddrc_set_regs(const unsigned long clk, const struct ddr_cfg_regs *regs, const struct ccsr_ddr *ddr, int twopass) { ... ... if (twopass == 2) goto after_reset; ... ... /* * For RDIMMs, JEDEC spec requires clocks to be stable before reset is * deasserted. Clocks start when any chip select is enabled and clock * control register is set. Because all DDR components are connected to * one reset signal, this needs to be done in two steps. Step 1 is to * get the clocks started. Step 2 resumes after reset signal is * deasserted. */ if (twopass == 1) { udelay(200); return 0; } after_reset: ... ... } static int write_ddrc_regs(struct ddr_info *priv) { int i; int ret; for (i = 0; i < priv->num_ctlrs; i++) { ret = ddrc_set_regs(priv->clk, &priv->ddr_reg, priv->ddr[i], 0); if (ret) { ERROR("Writing DDR register(s) failed\n"); return ret; } } return 0; }

My board is using UDIMM(no dimm) so it always use twopass=0 and the initialize will be like this:

START -> INIT DDRC1 -> WAIT DDRC1 -> INIT DDRC2 -> WAIT DDRC2 -> FINISH

So how to make the initialize sequence like below:

START -> INIT DDRC1 -> INIT DDRC2 -> WAIT DDRC1 -> WAIT DDRC2 -> FINISH

the twopass=1/2 is only for RDIMM, when force use twopass=1/2, it always get stuck.

Anyone can help let me know how to deal it?

Re: How to initialize two DDRC in parallel with UDIMM(no dimm) in LX2160

June_Lu — Mon, 02 Sep 2024 07:27:27 GMT

From the write_ddrc_regs, every controller is initialed independently.

twopass=1/2 is only for RDIMM, not for the different controllers.

Re: How to initialize two DDRC in parallel with UDIMM(no dimm) in LX2160

Zburid — Mon, 02 Sep 2024 12:00:03 GMT

Hi June, thanks for your reply. So there is no way for optimize the ATF in ddrc training stage?

Re: How to initialize two DDRC in parallel with UDIMM(no dimm) in LX2160

June_Lu — Wed, 04 Sep 2024 02:18:16 GMT

For the LSDK this is not support. And it's not validated.

For the other feature that LSDK is not included, maybe customer could validate themselves.

Thanks

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How to initialize two DDRC in parallel with UDIMM(no dimm) in LX2160

Re: How to initialize two DDRC in parallel with UDIMM(no dimm) in LX2160

Re: How to initialize two DDRC in parallel with UDIMM(no dimm) in LX2160

Re: How to initialize two DDRC in parallel with UDIMM(no dimm) in LX2160