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    <title>topic Re: Clarification on Secure Boot Flow for LX2160A in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/Clarification-on-Secure-Boot-Flow-for-LX2160A/m-p/1937877#M14795</link>
    <description>&lt;P&gt;Do you mean fuse OPTMK?&lt;/P&gt;
&lt;P&gt;For development stage, please&lt;SPAN&gt;&amp;nbsp;do secure boot with the following process.&lt;/SPAN&gt;&lt;/P&gt;
&lt;OL&gt;
&lt;LI&gt;&lt;SPAN&gt; Enabling POVDD and only blow OTPMK to fuse array following below_OTPMK.txt.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt; Build secure boot firmware image and deploy it to the target board.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt; Use CCS to put the LX2160A in RSP and write SRKH in SFP mirror registers following ccs_secureboot.txt.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/OL&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 22 Aug 2024 02:14:10 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2024-08-22T02:14:10Z</dc:date>
    <item>
      <title>Clarification on Secure Boot Flow for LX2160A</title>
      <link>https://community.nxp.com/t5/Layerscape/Clarification-on-Secure-Boot-Flow-for-LX2160A/m-p/1934787#M14763</link>
      <description>&lt;P&gt;Dear NXP Team,&lt;BR /&gt;&lt;BR /&gt;I am writing to seek clarification regarding the secure boot process for the LX2160A. Based on my understanding, I have outlined the secure boot flow in the attached diagram. I would like to confirm if my interpretation aligns with the expected procedure.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="harisankar2001_0-1724046609414.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/293719i5EE375D043D27CE2/image-size/medium?v=v2&amp;amp;px=400" role="button" title="harisankar2001_0-1724046609414.png" alt="harisankar2001_0-1724046609414.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have attached the flowchart for your reference. Could you please review this flowchart and confirm if this is the correct process for implementing secure boot on the LX2160A?&lt;/P&gt;&lt;P&gt;Additionally, if there are any steps or details that I might have missed or misinterpreted, I would greatly appreciate your guidance.&lt;/P&gt;&lt;P&gt;Thank you for your support and assistance.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 19 Aug 2024 05:51:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Clarification-on-Secure-Boot-Flow-for-LX2160A/m-p/1934787#M14763</guid>
      <dc:creator>harisankar2001</dc:creator>
      <dc:date>2024-08-19T05:51:30Z</dc:date>
    </item>
    <item>
      <title>Re: Clarification on Secure Boot Flow for LX2160A</title>
      <link>https://community.nxp.com/t5/Layerscape/Clarification-on-Secure-Boot-Flow-for-LX2160A/m-p/1936137#M14777</link>
      <description>&lt;P&gt;During development stage, we recommend customer use CCS provided in CodeWarrior to connect to the target to write values to SRKH shadow registers.&lt;/P&gt;
&lt;P&gt;The user needs to program image to the target board before writing&amp;nbsp;SRKH.&lt;/P&gt;</description>
      <pubDate>Tue, 20 Aug 2024 09:36:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Clarification-on-Secure-Boot-Flow-for-LX2160A/m-p/1936137#M14777</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2024-08-20T09:36:49Z</dc:date>
    </item>
    <item>
      <title>Re: Clarification on Secure Boot Flow for LX2160A</title>
      <link>https://community.nxp.com/t5/Layerscape/Clarification-on-Secure-Boot-Flow-for-LX2160A/m-p/1936995#M14784</link>
      <description>&lt;P&gt;Hi&amp;nbsp; yipingwang,&lt;/P&gt;&lt;P&gt;Thank you for your prompt response. We are currently working on a custom board based on the LX2160A.&lt;/P&gt;&lt;P&gt;I have one additional question regarding the secure boot process. In my previous message, I attached a flowchart detailing the process. Could you please clarify whether the fusing process for the public and private keys follows the same procedure, or if there are different steps involved for fusing the private key? If they differ, I would greatly appreciate it if you could share the specific steps required for private key fusing.&lt;/P&gt;&lt;P&gt;Thank you for your support.&lt;/P&gt;</description>
      <pubDate>Wed, 21 Aug 2024 05:32:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Clarification-on-Secure-Boot-Flow-for-LX2160A/m-p/1936995#M14784</guid>
      <dc:creator>harisankar2001</dc:creator>
      <dc:date>2024-08-21T05:32:04Z</dc:date>
    </item>
    <item>
      <title>Re: Clarification on Secure Boot Flow for LX2160A</title>
      <link>https://community.nxp.com/t5/Layerscape/Clarification-on-Secure-Boot-Flow-for-LX2160A/m-p/1937877#M14795</link>
      <description>&lt;P&gt;Do you mean fuse OPTMK?&lt;/P&gt;
&lt;P&gt;For development stage, please&lt;SPAN&gt;&amp;nbsp;do secure boot with the following process.&lt;/SPAN&gt;&lt;/P&gt;
&lt;OL&gt;
&lt;LI&gt;&lt;SPAN&gt; Enabling POVDD and only blow OTPMK to fuse array following below_OTPMK.txt.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt; Build secure boot firmware image and deploy it to the target board.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt; Use CCS to put the LX2160A in RSP and write SRKH in SFP mirror registers following ccs_secureboot.txt.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/OL&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 22 Aug 2024 02:14:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Clarification-on-Secure-Boot-Flow-for-LX2160A/m-p/1937877#M14795</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2024-08-22T02:14:10Z</dc:date>
    </item>
    <item>
      <title>Re: Clarification on Secure Boot Flow for LX2160A</title>
      <link>https://community.nxp.com/t5/Layerscape/Clarification-on-Secure-Boot-Flow-for-LX2160A/m-p/2032356#M15301</link>
      <description>&lt;P&gt;Hi yipingwang,&lt;BR /&gt;&lt;BR /&gt;Thank you for your response.&lt;/P&gt;&lt;P&gt;We are currently conducting a demo on the LA1224RDB board. Could you please clarify whether it is feasible to implement secure boot on the LA1224RDB board? Alternatively, if full secure boot implementation is not supported on this board, would it be possible to only boot the secure boot process?&lt;/P&gt;&lt;P&gt;Looking forward to your guidance.&lt;/P&gt;</description>
      <pubDate>Wed, 22 Jan 2025 12:40:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Clarification-on-Secure-Boot-Flow-for-LX2160A/m-p/2032356#M15301</guid>
      <dc:creator>harisankar2001</dc:creator>
      <dc:date>2025-01-22T12:40:00Z</dc:date>
    </item>
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