topic Re: LX2160A boot sequence in Layerscape

LX2160A boot sequence

Nikhiln — Thu, 27 Jun 2024 06:19:50 GMT

Hi,

We are using LX2160A processor in our custom board. Im facing issue in getting the processor to boot stage. Processor is unable to boot HRESET is high, but DDR reset from processor is low. What is the proper boot sequence of LX2160A? When processor starts DDR training?

My understanding is that the Processor loads RCW, then it looks for PBI image. If PBI or PBL image is not present it starts to boot (after RCW loading completion it should start DDR training). Is this correct?

Thanks

Nikhil N

Re: LX2160A boot sequence

yipingwang — Tue, 02 Jul 2024 02:39:39 GMT

Processor loads RCW and execute commands in PBI image, then executes ATF BL2 image in OCRAM. BL2 initializes DDR controller and copies BL31 to DDR memory and jumps the execution to BL31.

So as normal you should get the output of BL2 on the target board before DDR initialization.

Re: LX2160A boot sequence

Nikhiln — Mon, 08 Jul 2024 06:27:00 GMT

I have checked we are not getting any UART prints from UART 1, also no activity in UART 0 is observed. I have few doubts about this.

Does this mean Processor is not executing BL2 image or not reached that stage?

Do we get any output while executing PBI image?

HRESET is going high, this means RCW is correct and it has started executing PBI image, what if there is no PBI commands to execute? does it jump to executing BL2 or what happens?

how can I change the default UART port to UART 1 initially itself?

Re: LX2160A boot sequence

yipingwang — Tue, 09 Jul 2024 03:52:58 GMT

Please refer to the procedure I just provided in https://community.nxp.com/t5/Layerscape/Unable-to-boot-LX2160A-processor-out-of-PBI-and-DDR-reset-is-low/m-p/1902738/highlight/false#M14528

to deploy ATF images on your target board to check whether there is output from the UART.