topic Re: Possible cache coherency issue due to Cortex-A72 erratum on LS1046 in Layerscape

Possible cache coherency issue due to Cortex-A72 erratum on LS1046

Mughees — Tue, 23 Apr 2024 18:57:59 GMT

Arm has an erratum (Cortex-A72 MPCore Software Developers Errata Notice Version 11.0 (arm.com)) for Cortex-A72 that says:

"854172: An External Data Snoop Might Cause Data Corruption When An Evict Transaction Is Pending"

I would like to know if this erratum applies to LS1046 processors as well and if the workaround is implemented in the firmware, bootloader etc.?

Re: Possible cache coherency issue due to Cortex-A72 erratum on LS1046

LFGP — Wed, 24 Apr 2024 18:13:52 GMT

The mentioned ARM Errata is not affecting to the LS1046A due NXP doesn't have the configuration mentioned by ARM , read below:

854172: An external data snoop might cause data corruption when an Evict transaction is pending
Category C

Configurations affected
Systems using a non-ARM CHI-based interconnect that implement a snoop filter that can track cache lines with Shared Clean (SC) state to the precise CPU cluster.

Re: Possible cache coherency issue due to Cortex-A72 erratum on LS1046

Mughees — Wed, 24 Apr 2024 19:06:42 GMT

Hi,

Thank you so much for clearing this out.

Best Regards,

Mughees