topic IFC interface in Layerscape

topic IFC interface in Layerscape https://community.nxp.com/t5/Layerscape/IFC-interface/m-p/1838209#M14138 <P>Our IFC interface implementation for CPU and NAND flash will include connection to FPGA on the same lines for IFC.</P><P> </P><P>And Chip selects (CSn)  will be routed to FPGA and NAND flash,  for control.</P><P> </P><P>This connection concept is implemented in NXP EVB schematic.</P><P> </P><P>Please confirm that this interface is validate.   </P> Sun, 31 Mar 2024 12:51:52 GMT Roei89 2024-03-31T12:51:52Z IFC interface https://community.nxp.com/t5/Layerscape/IFC-interface/m-p/1838209#M14138 <P>Our IFC interface implementation for CPU and NAND flash will include connection to FPGA on the same lines for IFC.</P><P> </P><P>And Chip selects (CSn)  will be routed to FPGA and NAND flash,  for control.</P><P> </P><P>This connection concept is implemented in NXP EVB schematic.</P><P> </P><P>Please confirm that this interface is validate.   </P> Sun, 31 Mar 2024 12:51:52 GMT https://community.nxp.com/t5/Layerscape/IFC-interface/m-p/1838209#M14138 Roei89 2024-03-31T12:51:52Z