LayerscapeのトピックRe: Interrupt low time for ARMv8-A53 https://community.nxp.com/t5/Layerscape/Interrupt-low-time-for-ARMv8-A53/m-p/554842#M1408 <HTML><HEAD></HEAD><BODY><P>What is the best and worst case latency for interrupts on the LS1043A?&nbsp; Latency between the occurrences of the interrupt and the start of the ISR.</P></BODY></HTML> Thu, 23 Jun 2016 00:05:17 GMT pro-supportengi 2016-06-23T00:05:17Z Interrupt low time for ARMv8-A53 https://community.nxp.com/t5/Layerscape/Interrupt-low-time-for-ARMv8-A53/m-p/554840#M1406 <HTML><HEAD></HEAD><BODY><P>I want to now what is the minimum low time required for the ARMv8-A53 interrupt to detect as a valid interrupt.</P><P>Pls guide with proper reference.</P><P></P><P>For example, the ethernet driver for the LS1043ARDB and/or toggling a GPIO for an interrupt?</P></BODY></HTML> Tue, 21 Jun 2016 08:36:23 GMT https://community.nxp.com/t5/Layerscape/Interrupt-low-time-for-ARMv8-A53/m-p/554840#M1406 pro-supportengi 2016-06-21T08:36:23Z Re: Interrupt low time for ARMv8-A53 https://community.nxp.com/t5/Layerscape/Interrupt-low-time-for-ARMv8-A53/m-p/554841#M1407 <HTML><HEAD></HEAD><BODY><P>Have a great day,<BR /> </P><P>The LS1043A interrupt controller (GIC) inputs are asynchronous to any visible clock. GIC inputs are required to be valid for at least 3 SYSCLKs to ensure proper operation.</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Wed, 22 Jun 2016 06:38:36 GMT https://community.nxp.com/t5/Layerscape/Interrupt-low-time-for-ARMv8-A53/m-p/554841#M1407 r8070z 2016-06-22T06:38:36Z Re: Interrupt low time for ARMv8-A53 https://community.nxp.com/t5/Layerscape/Interrupt-low-time-for-ARMv8-A53/m-p/554842#M1408 <HTML><HEAD></HEAD><BODY><P>What is the best and worst case latency for interrupts on the LS1043A?&nbsp; Latency between the occurrences of the interrupt and the start of the ISR.</P></BODY></HTML> Thu, 23 Jun 2016 00:05:17 GMT https://community.nxp.com/t5/Layerscape/Interrupt-low-time-for-ARMv8-A53/m-p/554842#M1408 pro-supportengi 2016-06-23T00:05:17Z