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    <title>LayerscapeのトピックRe: FPGA configuring with LS1043</title>
    <link>https://community.nxp.com/t5/Layerscape/FPGA-configuring-with-LS1043/m-p/1808969#M13992</link>
    <description>Thank you for the verifying!</description>
    <pubDate>Thu, 15 Feb 2024 09:02:34 GMT</pubDate>
    <dc:creator>AntoNico10</dc:creator>
    <dc:date>2024-02-15T09:02:34Z</dc:date>
    <item>
      <title>FPGA configuring with LS1043</title>
      <link>https://community.nxp.com/t5/Layerscape/FPGA-configuring-with-LS1043/m-p/1803398#M13954</link>
      <description>&lt;P&gt;Hello everyone,&lt;/P&gt;&lt;P&gt;I'm planning to use the NXP LS1043 processor for a project that involves configuring a Xilinx Kintex UltraScale+ FPGA through the Passive Serial (PS) configuration mode. I'm curious about the feasibility of this setup and have a couple of questions:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Is it possible to configure the Xilinx Kintex UltraScale+ FPGA via Passive Serial using the LS1043 processor?&lt;/LI&gt;&lt;LI&gt;For the configuration process, can I use generic I/O pins on the LS1043, or are there specific pins that I need to utilize for this purpose?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Any insights or guidance on how to achieve this configuration would be greatly appreciated. If anyone has experience with a similar setup or can provide documentation or examples, that would be extremely helpful.&lt;/P&gt;&lt;P&gt;Thank you in advance for your assistance!&lt;/P&gt;</description>
      <pubDate>Wed, 07 Feb 2024 13:37:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/FPGA-configuring-with-LS1043/m-p/1803398#M13954</guid>
      <dc:creator>AntoNico10</dc:creator>
      <dc:date>2024-02-07T13:37:51Z</dc:date>
    </item>
    <item>
      <title>Re: FPGA configuring with LS1043</title>
      <link>https://community.nxp.com/t5/Layerscape/FPGA-configuring-with-LS1043/m-p/1804860#M13972</link>
      <description>&lt;P&gt;Yes it could be done using the LS1043. There isn't specific pins for your purpose so you can use the GIOP's or use the JTAG's pins.&lt;/P&gt;
&lt;P&gt;Unfortunately we don't have any example of it.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 09 Feb 2024 18:07:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/FPGA-configuring-with-LS1043/m-p/1804860#M13972</guid>
      <dc:creator>LFGP</dc:creator>
      <dc:date>2024-02-09T18:07:17Z</dc:date>
    </item>
    <item>
      <title>Re: FPGA configuring with LS1043</title>
      <link>https://community.nxp.com/t5/Layerscape/FPGA-configuring-with-LS1043/m-p/1808969#M13992</link>
      <description>Thank you for the verifying!</description>
      <pubDate>Thu, 15 Feb 2024 09:02:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/FPGA-configuring-with-LS1043/m-p/1808969#M13992</guid>
      <dc:creator>AntoNico10</dc:creator>
      <dc:date>2024-02-15T09:02:34Z</dc:date>
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